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1. (WO2018042846) ELECTRONIC DEVICE AND MULTILAYER CERAMIC SUBSTRATE
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Pub. No.: WO/2018/042846 International Application No.: PCT/JP2017/023542
Publication Date: 08.03.2018 International Filing Date: 27.06.2017
IPC:
H05K 1/18 (2006.01) ,H01L 21/60 (2006.01) ,H01L 23/13 (2006.01) ,H05K 3/34 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
18
Printed circuits structurally associated with non-printed electric components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
34
by soldering
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
岡 隆宏 OKA, Takahiro; JP
武森 祐貴 TAKEMORI, Yuki; JP
岸田 和雄 KISHIDA, Kazuo; JP
川上 弘倫 KAWAKAMI, Hiromichi; JP
山本 幸男 YAMAMOTO, Yukio; JP
大竹 健介 OTAKE, Kensuke; JP
Agent:
特許業務法人 安富国際特許事務所 YASUTOMI & ASSOCIATES; 大阪府大阪市淀川区宮原3丁目5番36号 5-36, Miyahara 3-chome, Yodogawa-ku, Osaka-shi, Osaka 5320003, JP
Priority Data:
2016-16831430.08.2016JP
Title (EN) ELECTRONIC DEVICE AND MULTILAYER CERAMIC SUBSTRATE
(FR) DISPOSITIF ÉLECTRONIQUE ET SUBSTRAT CÉRAMIQUE MULTICOUCHE
(JA) 電子デバイス及び多層セラミック基板
Abstract:
(EN) This electronic device comprises a substrate with an electronic component mounted thereon, wherein the electronic component is provided with a connection terminal on a mounting surface side thereof, the connection terminal being R-shaped when observed in cross-section view. This multilayer ceramic substrate comprises a surface electrode for connecting to the connection terminal, and is characterized in that: a recess is provided on a mounting surface of the multilayer ceramic substrate, the recess being R-shaped when observed in cross-section view and being formed at a position that corresponds to the connection terminal; and the surface electrode is provided to at least a portion of the recess, and is conductive with the connection terminal.
(FR) La présente invention concerne un dispositif électronique qui comprend un substrat sur lequel est monté un composant électronique, le composant électronique comportant une borne de connexion de son côté de surface de montage, la borne de connexion ayant une forme de R lorsqu’on l’observe en vue de section transversale. Ce substrat céramique multicouche comprend une électrode de surface pour la connexion à la borne de connexion, et est caractérisé : en qu’un évidement est creusé sur une surface de montage du substrat céramique multicouche, l’évidement ayant une forme de R lorsqu’il est observé en vue de section transversale et étant formé à une position qui correspond à la borne de connexion ; et en ce que l’électrode de surface est fournie à au moins une partie de l’évidement et est conductrice avec la borne de connexion.
(JA) 本発明の電子デバイスは、多層セラミック基板に電子部品が実装された電子デバイスであって、上記電子部品は、断面視でR形状を有する接続端子を実装面側に備え、上記多層セラミック基板は、上記接続端子と接続するための表面電極を備え、上記多層セラミック基板の実装面には、上記接続端子に対応する位置に、断面視でR形状を有する凹部が形成されており、上記表面電極は、上記凹部の少なくとも一部に設けられており、上記接続端子と導通していることを特徴とする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)