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1. (WO2018042835) SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
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Pub. No.: WO/2018/042835 International Application No.: PCT/JP2017/022651
Publication Date: 08.03.2018 International Filing Date: 20.06.2017
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/12 (2006.01) ,H01L 29/417 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
Applicants:
住友電気工業株式会社 SUMITOMO ELECTRIC INDUSTRIES, LTD. [JP/JP]; 大阪府大阪市中央区北浜四丁目5番33号 5-33, Kitahama 4-chome, Chuo-ku, Osaka-shi, Osaka 5410041, JP
Inventors:
内田 光亮 UCHIDA, Kosuke; JP
日吉 透 HIYOSHI, Toru; JP
酒井 光彦 SAKAI, Mitsuhiko; JP
Agent:
特許業務法人深見特許事務所 FUKAMI PATENT OFFICE, P.C.; 大阪府大阪市北区中之島三丁目2番4号 中之島フェスティバルタワー・ウエスト Nakanoshima Festival Tower West, 2-4, Nakanoshima 3-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
Priority Data:
2016-16962431.08.2016JP
Title (EN) SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR AU CARBURE DE SILICIUM ET SON PROCÉDÉ DE FABRICATION
(JA) 炭化珪素半導体装置およびその製造方法
Abstract:
(EN) A gate trench, which is defined by a first side surface and a first bottom surface, and a source trench, which is defined by a second side surface and a second bottom surface, are provided on a first main surface. A silicon carbide substrate includes a drift region, body region, source region, first region, and second region. The first region is in contact with the second region. On the first side surface, a gate insulating film is in contact with the drift region, the body region, and the source region, and on the first bottom surface, the gate insulating film is in contact with the drift region. On the second side surface and the second bottom surface, the source electrode is in contact with the second region.
(FR) La présente invention concerne une tranchée de grille, qui est définie par une première surface latérale et une première surface inférieure, et une tranchée source, qui est définie par une seconde surface latérale et une seconde surface inférieure, étant disposées sur une première surface principale. Un substrat de carbure de silicium comprend une région de dérive, une région de corps, une région de source, une première région et une seconde région. La première région est en contact avec la seconde région. Sur la première surface latérale, un film d'isolation de grille est en contact avec la région de dérive, la région de corps, et la région source, et sur la première surface inférieure, le film isolant de grille est en contact avec la région de dérive. Sur la seconde surface latérale et la seconde surface inférieure, l'électrode source est en contact avec la seconde région.
(JA) 第1主面には、第1側面と、第1底面とにより規定されているゲートトレンチと、第2側面と、第2底面とにより規定されているソーストレンチとが設けられている。炭化珪素基板は、ドリフト領域と、ボディ領域と、ソース領域と、第1領域と、第2領域とを含む。第1領域は、第2領域と接する。ゲート絶縁膜は、第1側面において、ドリフト領域と、ボディ領域と、ソース領域と接し、かつ第1底面において、ドリフト領域に接している。ソース電極は、第2側面と第2底面とにおいて、第2領域と接している。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)