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1. (WO2018041082) DEVICE INTEGRATING JUNCTION FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/041082 International Application No.: PCT/CN2017/099402
Publication Date: 08.03.2018 International Filing Date: 29.08.2017
IPC:
H01L 27/02 (2006.01) ,H01L 27/06 (2006.01) ,H01L 29/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Applicants: CSMC TECHNOLOGIES FAB2 CO., LTD.[CN/CN]; No.8 Xinzhou Road Wuxi New District, Jiangsu 214028, CN
Inventors: GU, Yan; CN
CHENG, Shikang; CN
ZHANG, Sen; CN
Agent: ADVANCE CHINA IP LAW OFFICE; Room 3901, No. 85 Huacheng Avenue, Tianhe District Guangzhou, Guangdong 510623, CN
Priority Data:
201610793753.131.08.2016CN
Title (EN) DEVICE INTEGRATING JUNCTION FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR
(FR) DISPOSITIF INTÉGRANT UN TRANSISTOR À EFFET DE CHAMP À JONCTION ET SON PROCÉDÉ DE FABRICATION
(ZH) 集成有结型场效应晶体管的器件及其制造方法
Abstract:
(EN) A device integrating a junction field-effect transistor (JFET), comprising: a drain electrode (201), having a first conductivity type, a portion of the drain electrode (201) being in a JFET region and the other portion being in a power device region; a first conductivity type region (214), disposed on a front surface of the drain electrode (201), a portion of the first conductivity type region (214) being located in the JFET region and the other portion being located in the power device region. The JFET region comprises: a JFET source electrode (208), having a first conductivity type; a metal electrode (212), formed on the JFET source electrode (208) and in contact with the JFET source electrode (208); composite well region structures, having a second conductivity type and being disposed in the first conductivity type region (214), the composite well region structures comprising a first well (202) and a second well (205) located in the first well (202), the ion concentration of the second well (205) being greater than the ion concentration of the first well (202). A composite well region structure is formed on each of two sides of the JFET source electrode (208), the JFET source electrode (208) extending laterally into the first well (202) and the second well (205), and the first conductivity type being opposite to the second conductivity type; and a JFET metal grid electrode (213), disposed on the composite well structures on both sides of the JFET source electrode (208).
(FR) Un dispositif intégrant un transistor à effet de champ à jonction (JFET) comprend : une électrode de drain (201), ayant un premier type de conductivité, une portion de l'électrode de drain (201) étant dans une région JFET et l'autre portion étant dans une région de dispositif d'alimentation; une région de premier type de conductivité (214), disposée sur une surface avant de l'électrode de drain (201), une portion de la région de premier type de conductivité (214) étant située dans la région JFET et l'autre portion étant située dans la région de dispositif d'alimentation. La région JFET comprend : une électrode de source JFET (208), ayant un premier type de conductivité; une électrode métallique (212), formée sur l'électrode de source JFET (208) et en contact avec l'électrode de source JFET (208); des structures de région de puits composite, ayant un second type de conductivité et étant disposées dans la région de premier type de conductivité (214), les structures de région de puits composites comprenant un premier puits (202) et un second puits (205) situé dans le premier puits (202), la concentration ionique du second puits (205) étant supérieure à la concentration ionique du premier puits (202). Une structure de région de puits composite est formée sur chacun des deux côtés de l'électrode de source JFET (208), l'électrode de source JFET (208) s'étendant latéralement dans le premier puits (202) et le second puits (205), et le premier type de conductivité étant opposé au second type de conductivité; et une électrode de grille métallique JFET (213), disposée sur les structures de puits composites sur les deux côtés de l'électrode de source JFET (208).
(ZH) 一种集成有结型场效应晶体管的器件,包括:漏极(201),具有第一导电类型,漏极(201)的一部分位于JFET区、另一部分位于功率器件区;及第一导电类型区(214),设于漏极(201)的正面,第一导电类型区(214)的一部分位于JFET区、另一部分位于功率器件区;JFET区包括:JFET源极(208),具有第一导电类型;金属电极(212),形成于JFET源极(208)上与JFET源极(208)接触;及复合阱区结构,具有第二导电类型且设于第一导电类型区(214)内,复合阱区结构包括第一阱(202)和位于第一阱(202)内的第二阱(205),第二阱(205)的离子浓度大于第一阱(202)的离子浓度,复合阱区结构在JFET源极(208)的两侧各形成有一个,且JFET源极(208)横向延伸进入第一阱(202)和第二阱(205)内;第一导电类型和第二导电类型相反;及JFET金属栅极(213),设于JFET源极(208)两侧的复合阱区结构上。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)