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1. (WO2018040489) ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR
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Pub. No.: WO/2018/040489 International Application No.: PCT/CN2017/071600
Publication Date: 08.03.2018 International Filing Date: 18.01.2017
IPC:
H01L 27/12 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号 No.9-2, Tangming Road, Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
曾勉 ZENG, Mian; CN
Agent:
北京聿宏知识产权代理有限公司 YUHONG INTELLECTUAL PROPERTY LAW FIRM; 中国北京市 西城区宣武门外大街6号庄胜广场第一座西翼713室吴大建/王浩 WU Dajian/WANG Hao West Wing, Suite 713, One Junefield Plaza, 6 Xuanwumenwai Street, Xicheng District Beijing 100052, CN
Priority Data:
201610799421.431.08.2016CN
Title (EN) ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR
(FR) SUBSTRAT MATRICIEL ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 一种阵列基板及其制备方法
Abstract:
(EN) An array substrate and a preparation method therefor. The array substrate comprises a transmission gate structure. The transmission gate structure comprises two, i.e. upper and lower, TFTs; an active layer of the TFT located at a lower side is a first active layer (4), and an active layer of the TFT located at an upper side is a second active layer (8); and the first active layer (4) and the second active layer (8) are respectively arranged at two sides of source and drain electrode layers (7), and share source and drain electrodes. This structure is beneficial for simplifying the preparation process of a transmission gate structure, and improves the preparation success rate.
(FR) La présente invention concerne un substrat matriciel et son procédé de préparation. Le substrat matriciel comprend une structure de grille de transmission. La structure de grille de transmission comprend deux TFT, c'est-à-dire des TFT supérieur et inférieur; une couche active du TFT située au niveau d'un côté inférieur est une première couche active (4), et une couche active du TFT située au niveau d'un côté supérieur est une seconde couche active (8); et la première couche active (4) et la seconde couche active (8) sont respectivement agencées au niveau de deux côtés de couches d'électrode de source et de drain (7), et partagent des électrodes de source et de drain. Cette structure est avantageuse pour simplifier le processus de préparation d'une structure de grille de transmission, et améliore le taux de réussite de préparation.
(ZH) 一种阵列基板及其制备方法,该阵列基板包括一种传输门结构。传输门结构包括上下两个TFT,位于下侧的TFT的有源层为第一有源层(4),位于上侧的TFT的有源层为第二有源层(8),第一有源层(4)和第二有源层(8)分别设置在源漏极层(7)的两侧,共用源漏电极。这个结构有利于简化传输门结构的制备工艺,提高制备的成功率。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)