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1. (WO2018040327) ON-CHIP TDDB DEGRADATION MONITORING AND FAILURE WARNING CIRCUIT FOR SOC

Pub. No.:    WO/2018/040327    International Application No.:    PCT/CN2016/107700
Publication Date: Fri Mar 09 00:59:59 CET 2018 International Filing Date: Wed Nov 30 00:59:59 CET 2016
IPC: G01R 31/14
Applicants: FIFTH ELECTRONICS RESEARCH INSTITUTE OF MINISTRY OF INDUSTRY AND INFORMATION TECHNOLOGY
工业和信息化部电子第五研究所
Inventors: CHEN, Yiqiang
陈义强
LEI, Dengyun
雷登云
EN, Yunfei
恩云飞
FANG, Wenxiao
方文啸
HAO, Lichao
郝立超
HUANG, Yun
黄云
HOU, Bo
侯波
LU, Yudong
陆裕东
Title: ON-CHIP TDDB DEGRADATION MONITORING AND FAILURE WARNING CIRCUIT FOR SOC
Abstract:
An on-chip TDDB degradation monitoring and failure warning circuit for a SoC. A control circuit module (200) converts Q1 and Q0 signals into switch state control signals and outputs same to a TDDB performance degradation digital conversion module (300). An MOS tube of a first MOS tube circuit in the TDDB performance degradation digital conversion module (300) is in a stress state of a power voltage, and an MOS tube of a second MOS tube circuit is in a non-stress state. The first MOS tube circuit and the second MOS tube circuit respectively output a first frequency value and a second frequency value to an output selection module (400) under the control of the switch state control signals. The output selection module (400) outputs the first frequency value output by the TDDB performance degradation digital conversion module (300) to a counter B for recording, or outputs the second frequency value to a counter A for recording. A counter module (500) compares the first frequency value with the second frequency value and determines the degradation degree of a TDDB performance. The circuit is simple in structure, a TDDB performance degradation process can be monitored by means of outputs, and the TDDB performance can be accurately early warned.