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1. (WO2018040287) THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.:    WO/2018/040287    International Application No.:    PCT/CN2016/105433
Publication Date: 08.03.2018 International Filing Date: 11.11.2016
IPC:
H01L 29/786 (2006.01), H01L 21/336 (2006.01), H01L 29/06 (2006.01)
Applicants: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; No.9-2, Tangming Road, Guangming New District Shenzhen, Guangdong 518132 (CN)
Inventors: ZHAI, Yuhao; (CN)
Agent: YUHONG INTELLECTUAL PROPERTY LAW FIRM; WU, Dajian/ LIU, Hualian West Wing, Suite 713, One Junefield Plaza, 6 Xuanwumenwai Street, Xicheng District Beijing 100052 (CN)
Priority Data:
201610778598.6 31.08.2016 CN
Title (EN) THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR
(FR) TRANSISTOR À COUCHES MINCES ET PROCÉDÉ POUR SA FABRICATION
(ZH) 薄膜晶体管及其制作方法
Abstract: front page image
(EN)Provided is a thin film transistor. An anti-damage layer (30) is provided between an active layer (10) and a source electrode (20) of the thin film transistor; and an anti-damage layer (30) is provided between the active layer (10) and a drain electrode (40). The thin film transistor is simple in structure. By means of providing an anti-damage layer (30) between an active layer (10) and a source electrode (20) of the thin film transistor and providing an anti-damage layer (30) between the active layer (10) and a drain electrode (40) of the thin film transistor, the channel length can be effectively reduced, and a parasitic capacitance between the source electrode (20) and a gate electrode (70) and a parasitic capacitance between the drain electrode (40) and the gate electrode (70) can be reduced.
(FR)L'invention concerne un transistor à couches minces. Une couche anti-endommagement (30) est disposée entre une couche active (10) et une électrode de source (20) du transistor à couches minces; et une couche anti-endommagement (30) est disposée entre la couche active (10) et une électrode de drain (40). Le transistor à couches minces est de structure simple. Au moyen de la fourniture d'une couche anti-endommagement (30) entre une couche active (10) et une électrode de source (20) du transistor à couches minces et fournir une couche anti-endommagement (30) entre la couche active (10) et une électrode de drain (40) du transistor à couches minces, la longueur de canal peut être efficacement réduite, et une capacité parasite entre l'électrode de source (20) et une électrode de grille (70) et une capacité parasite entre l'électrode de drain (40) et l'électrode de grille (70) peuvent être réduites.
(ZH)提供一种薄膜晶体管,其中薄膜晶体管的有源层(10)和源极(20)之间设有防损伤层(30),有源层(10)和漏极(40)之间设有防损伤层(30)。该薄膜晶体管结构简单,通过在薄膜晶体管的有源层(10)和源极(20)之间设有防损伤层(30)及薄膜晶体管的有源层(10)和漏极(40)之间设有防损伤层(30),能够有效的减小沟道长度,并且降低源极(20)和栅极(70)之间的寄生电容和降低漏极(40)和栅极(70)之间的寄生电容。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)