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1. (WO2018039645) INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED FABRICATION TECHNIQUES
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Pub. No.: WO/2018/039645 International Application No.: PCT/US2017/048752
Publication Date: 01.03.2018 International Filing Date: 25.08.2017
IPC:
H01L 31/18 (2006.01) ,H01L 31/042 (2006.01) ,H02S 20/20 (2014.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
18
Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
04
adapted as conversion devices
042
including a panel or array of photoelectric cells, e.g. solar cells
[IPC code unknown for H02S 20/20]
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, CA 95054, US
Inventors:
BLOCK, Bruce; US
RAO, Valluri R.; US
MEHANDRU, Rishabh; US
INGERLY, Doug; US
JUN, Kimin; US
O'BRIEN, Kevin; US
MORROW, Patrick; US
FISCHER, Paul; US
LIAO, Szyua S.; US
Agent:
HOWARD, James M.; US
Priority Data:
62/380,31626.08.2016US
PCT/US16/6856423.12.2016US
PCT/US17/4847524.08.2017US
Title (EN) INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED FABRICATION TECHNIQUES
(FR) STRUCTURES DE DISPOSITIF À CIRCUIT INTÉGRÉ ET TECHNIQUES DE FABRICATION À DOUBLE FACE
Abstract:
(EN) Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
(FR) L'invention concerne des architectures de cellules de circuit intégré comprenant à la fois des structures face avant et face arrière. Un ou plusieurs parmi l'implant face arrière, le dépôt de semi-conducteur, le dépôt diélectrique, la métallisation, la formation de film et le transfert de couche de niveau de tranche est intégré avec un traitement face avant. Un tel traitement double face peut consister à révéler une face arrière de structures fabriquées à partir de la face avant d'un substrat. Des assemblages substrats donneurs-hôtes peuvent être construits pour supporter et protéger des structures face avant pendant un traitement face arrière. Des dispositifs face avant, tels que des FET, peuvent être modifiés et/ou interconnectés pendant un traitement face arrière. Des dispositifs face arrière, tels que des FET, peuvent être intégrés à des dispositifs face avant pour étendre une fonctionnalité de dispositif, améliorer les performances, ou augmenter la densité de dispositif.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)