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1. (WO2018039156) ERROR CORRECTION HARDWARE WITH FAULT DETECTION

Pub. No.:    WO/2018/039156    International Application No.:    PCT/US2017/047890
Publication Date: Fri Mar 02 00:59:59 CET 2018 International Filing Date: Wed Aug 23 01:59:59 CEST 2017
IPC: G06F 11/16
G11C 29/42
B60W 30/00
Applicants: TEXAS INSTRUMENTS INCORPORATED
TEXAS INSTRUMENTS JAPAN LIMITED
Inventors: JALAN, Saket
PRATHAPAN, Indu
KARKISAVAL, Abhishek, Ganapati
Title: ERROR CORRECTION HARDWARE WITH FAULT DETECTION
Abstract:
In described examples, error correction code (ECC) hardware includes write generation (Gen) ECC logic (115b) and a check ECC block (120b) coupled to an ECC output of a memory circuit (130) with read Gen ECC logic (120b1) coupled to an XOR circuit (120b2) that outputs a syndrome signal to a syndrome decode block (120c) coupled to a single bit error correction block (120d). A first MUX (115a) receives the write data and is in series with an input to the write Gen ECC logic (115b), or a second MUX (120e) receives the read data from the memory circuit (130) in series with an input of the read Gen ECC logic (120b1). A cross-coupling connector (150, 150') couples the read data from the memory circuit (130) to a second input of the first MUX (115a), or couples the write data to a second input of the second MUX (120e). An ECC bit comparator (135) compares an output of the write Gen ECC logic (115b) to the read Gen ECC logic output (120b1).