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1. (WO2018038865) METHODS OF FORMING A DEVICE HAVING SEMICONDUCTOR DEVICES ON TWO SIDES OF A BURIED DIELECTRIC LAYER
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Pub. No.: WO/2018/038865 International Application No.: PCT/US2017/044007
Publication Date: 01.03.2018 International Filing Date: 26.07.2017
Chapter 2 Demand Filed: 17.05.2018
IPC:
H01L 21/84 (2006.01) ,H01L 21/822 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
84
the substrate being other than a semiconductor body, e.g. being an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
GOKTEPELI, Sinan; US
FANELLI, Stephen Alan; US
Agent:
TOLER, Jeffrey G.; US
Priority Data:
15/249,11226.08.2016US
Title (EN) METHODS OF FORMING A DEVICE HAVING SEMICONDUCTOR DEVICES ON TWO SIDES OF A BURIED DIELECTRIC LAYER
(FR) PROCÉDÉS DE FORMATION D'UN DISPOSITIF AYANT DES DISPOSITIFS À SEMI-CONDUCTEUR SUR DEUX CÔTÉS D'UNE COUCHE DIÉLECTRIQUE ENTERRÉE
Abstract:
(EN) A method includes performing an etching process from a second side of a buried dielectric layer to expose an etch stop layer, where the second side of the buried dielectric layer is opposite a first side of the buried dielectric layer, and where a first semiconductor device is positioned on the first side of the buried dielectric layer. The method further includes forming a second semiconductor device on the second side of the buried dielectric layer.
(FR) L'invention concerne un procédé comprenant la réalisation d'un processus de gravure à partir d'un second côté d'une couche diélectrique enterrée pour exposer une couche d'arrêt de gravure, le second côté de la couche diélectrique enterrée étant opposé à un premier côté de la couche diélectrique enterrée, et un premier dispositif à semi-conducteur étant positionné sur le premier côté de la couche diélectrique enterrée. Le procédé comprend en outre la formation d'un second dispositif à semi-conducteur sur le second côté de la couche diélectrique enterrée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)