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1. (WO2018038817) INTEGRATED CLOCK GATE CIRCUIT WITH EMBEDDED NOR
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Pub. No.: WO/2018/038817 International Application No.: PCT/US2017/041702
Publication Date: 01.03.2018 International Filing Date: 12.07.2017
IPC:
H03K 3/037 (2006.01) ,H03K 3/356 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
027
by the use of logic circuits, with internal or external positive feedback
037
Bistable circuits
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
02
Generators characterised by the type of circuit or by the means used for producing pulses
353
by the use, as active elements, of field-effect transistors with internal or external positive feedback
356
Bistable circuits
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd Santa Clara, California 95054, US
Inventors:
HSU, Steven K.; US
AGARWAL, Amit; US
RAJWANI, Iqbal R.; US
REALOV, Simeon; US
KRISHNAMURTHY, Ram K.; US
Agent:
MUGHAL, Usman; US
Priority Data:
15/244,83923.08.2016US
Title (EN) INTEGRATED CLOCK GATE CIRCUIT WITH EMBEDDED NOR
(FR) CIRCUIT INTÉGRÉ DE GRILLE D’HORLOGE AVEC NI INTÉGRÉ
Abstract:
(EN) An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.
(FR) La présente invention concerne un appareil qui comprend : un nœud d’horloge ; un nœud de test ; un nœud de validation ; et un verrouillage statique d’inverseur ET-OU (AOI) couplé au nœud d’horloge, au nœud de test et au nœud de validation, le verrou statique AOI ayant une fonctionnalité NI intégrée. Un autre appareil comprend : un trajet de temporisation critique comportant une grille d’horloge intégrée à base de passe-grille ; et un trajet de temporisation non critique électriquement couplé au trajet de temporisation critique, le trajet de temporisation non critique comprenant une grille d’horloge intégrée basée sur un inverseur ET-OU (AOI) avec une fonctionnalité NI intégrée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)