Search International and National Patent Collections

1. (WO2018038813) LINK ERROR CORRECTION IN MEMORY SYSTEM

Pub. No.:    WO/2018/038813    International Application No.:    PCT/US2017/041129
Publication Date: Fri Mar 02 00:59:59 CET 2018 International Filing Date: Sat Jul 08 01:59:59 CEST 2017
IPC: G06F 11/10
Applicants: QUALCOMM INCORPORATED
Inventors: SUH, Jungwon
Title: LINK ERROR CORRECTION IN MEMORY SYSTEM
Abstract:
Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the burst length.