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1. (WO2018038598) MONOLITHIC ON-CHIP FINE TUNE SPIRAL INDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/038598 International Application No.: PCT/MY2017/050043
Publication Date: 01.03.2018 International Filing Date: 27.07.2017
Chapter 2 Demand Filed: 21.06.2018
IPC:
H01L 49/02 (2006.01) ,H01L 27/06 (2006.01) ,H01L 29/82 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02
Thin-film or thick-film devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
82
controllable by variation of the magnetic field applied to the device
Applicants: UNIVERSITI SAINS MALAYSIA[MY/MY]; Innovation Office, Division of Research and Innovation, Chancellory II, Block E42, USM Glugor, 11800, MY
SILTERRA MALAYSIA SDN BHD[MY/MY]; Lot 8, Industrial Zone Phase 2, Kulim Hi-tech Park, Kedah Kulim, 09000, MY
Inventors: MOHD. NOH, Norlaili; MY
ABD MANAF, Asrulnizam; MY
ESHGHABADI, Farshad; MY
BANITORFIAN, Fatemeh; MY
HASHIM, Awatif; MY
MUSTAFFA, Mohd Tafir; MY
SIDEK, Othman; MY
KUNHI MOHD, Shukri Korakkottil; MY
MOHD. YUSOF, Yusman; MY
Agent: PYPRUS SDN BHD; Unit 1608, 16th Floor, Block A, Damansara Intan, No. 1, Jalan SS20/27, Selangor Petaling Jaya, 47400, MY
Priority Data:
PI 201670305122.08.2016MY
Title (EN) MONOLITHIC ON-CHIP FINE TUNE SPIRAL INDUCTOR DEVICE
(FR) DISPOSITIF D'INDUCTEUR EN SPIRALE À ACCORD FIN MONOLITHIQUE SUR PUCE
Abstract:
(EN) A monolithic on-chip fine tune spiral inductor device comprises a semiconductor substrate including a plurality of metal layers; a plurality of peripheral metal grounds being formed in one of the metal layers and disposed at peripheral of the semiconductor substrate and connected to a perfect ground; a patterned metal shield formed in central portion of the semiconductor substrate on the same metal layer forming the peripheral metal grounds, wherein the patterned metal shield comprises a plurality of isolated metal slots, and the plurality of isolated metal slots are isolated from each other and switched individually or in a group; a conductive inductor loop having one or more turns overlying the patterned metal shield and being formed on a metal layer that is different from the one forming the peripheral metal grounds; and a plurality of switches electrically coupling the peripheral metal grounds to the metal slots of the patterned metal shield.
(FR) Un dispositif d'inducteur en spirale à accord fin monolithique sur puce comprend un substrat semi-conducteur comprenant une pluralité de couches métalliques; une pluralité de masses métalliques périphériques étant formées dans l'une des couches métalliques et disposées au niveau de la périphérie du substrat semi-conducteur et reliées à une masse parfaite; un blindage métallique à motifs formé dans une portion centrale du substrat semi-conducteur sur la même couche métallique formant les masses métalliques périphériques, le blindage métallique à motifs comprenant une pluralité de fentes métalliques isolées, et la pluralité de fentes métalliques isolées sont isolées les unes des autres et commutées individuellement ou dans un groupe; une boucle d'induction conductrice ayant une ou plusieurs spires recouvrant le blindage métallique à motifs et étant formée sur une couche métallique qui est différente de celle formant les masses métalliques périphériques; et une pluralité de commutateurs couplant électriquement les masses métalliques périphériques aux fentes métalliques du blindage métallique à motifs.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)