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1. (WO2018038098) MEMORY DEVICE
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Pub. No.: WO/2018/038098 International Application No.: PCT/JP2017/029923
Publication Date: 01.03.2018 International Filing Date: 22.08.2017
IPC:
H01L 21/336 (2006.01) ,H01L 27/10 (2006.01) ,H01L 27/11521 (2017.01) ,H01L 29/788 (2006.01) ,H01L 29/792 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
788
with floating gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
792
with charge trapping gate insulator, e.g. MNOS-memory transistor
Applicants:
国立研究開発法人科学技術振興機構 JAPAN SCIENCE AND TECHNOLOGY AGENCY [JP/JP]; 埼玉県川口市本町四丁目1番8号 4-1-8, Honcho, Kawaguchi-shi, Saitama 3320012, JP
Inventors:
中嶋 敦 NAKAJIMA Atsushi; JP
舘田 英加 TACHIDA Eika; JP
渡辺 義夫 WATANABE Yoshio; JP
平田 直之 HIRATA Naoyuki; JP
根岸 雄一 NEGISHI Yuichi; JP
佐藤 実奈子 SATO Minako; JP
角山 寛規 TSUNOYAMA Hironori; JP
横山 高穂 YOKOYAMA Takaho; JP
Agent:
志賀 正武 SHIGA Masatake; JP
鈴木 三義 SUZUKI Mitsuyoshi; JP
大槻 真紀子 OTSUKI Makiko; JP
Priority Data:
2016-16204822.08.2016JP
Title (EN) MEMORY DEVICE
(FR) DISPOSITIF DE MÉMOIRE
(JA) メモリデバイス
Abstract:
(EN) Provided is a memory device comprising, in this order: a semiconductor section (1); a first insulation layer (2); a charge retention layer (3); a second insulation layer (4); and an electrode (5). The charge retention layer mainly includes a nanocluster (30) of a predetermined number of atoms.
(FR) L'invention concerne un dispositif de mémoire comprenant, dans cet ordre : une section semi-conductrice (1); une première couche d'isolation (2); une couche de rétention de charge (3); une seconde couche d'isolation (4); et une électrode (5). La couche de rétention de charge comprend principalement un nanoagrégat (30) d'un nombre prédéterminé d'atomes.
(JA) 半導体部(1)と,第1絶縁層(2)と,電荷保持層(3)と,第2絶縁層(4)と,電極(5)とを順に備え,前記電荷保持層は,所定の原子数のナノクラスター(30)を主として含むメモリデバイスを提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)