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1. (WO2018037871) RESIN MULTILAYER SUBSTRATE, TRANSMISSION LINE, MODULE, AND METHOD FOR MANUFACTURING MODULE
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Pub. No.: WO/2018/037871 International Application No.: PCT/JP2017/028209
Publication Date: 01.03.2018 International Filing Date: 03.08.2017
IPC:
H05K 1/02 (2006.01) ,H05K 3/28 (2006.01) ,H05K 3/32 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
22
Secondary treatment of printed circuits
28
Applying non-metallic protective coatings
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
32
electrically connecting electric components or wires to printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
佐々木 純 SASAKI Jun; JP
齋藤 陽一 SAITO Yoichi; JP
馬場 貴博 BABA Takahiro; JP
松田 文絵 MATSUDA Fumie; JP
田中 良知 TANAKA Yoshitomo; JP
Agent:
特許業務法人 楓国際特許事務所 KAEDE PATENT ATTORNEYS' OFFICE; 大阪府大阪市中央区農人橋1丁目4番34号 1-4-34, Noninbashi, Chuo-ku, Osaka-shi, Osaka 5400011, JP
Priority Data:
2016-16633626.08.2016JP
Title (EN) RESIN MULTILAYER SUBSTRATE, TRANSMISSION LINE, MODULE, AND METHOD FOR MANUFACTURING MODULE
(FR) SUBSTRAT MULTICOUCHE EN RÉSINE, LIGNE DE TRANSMISSION, MODULE ET PROCÉDÉ DE FABRICATION DE MODULE
(JA) 樹脂多層基板、伝送線路、モジュールおよびモジュールの製造方法
Abstract:
(EN) A module (121), provided with a laminate (10) including a plurality of laminated insulating resin substrates (11, 12, 13, 14), the laminate (10) having a first main surface (S1) and a second main surface (S2) and having first regions (Z1) and second regions (Z2) in plan view. A first conductor pattern (31) and a protective film (21) covering the first conductor pattern (31) are formed in the first region (Z1) of the first main surface (S1). Second conductor patterns (32G, 32S1) and holes leading to the second conductor patterns (32G, 32S1) are formed in the second regions (Z2) of the laminate (10). Electroconductive adhesive materials (BG1, BG2, BS) are packed into the holes, and connectors (91, 92) are connected to the second conductor patterns via the electroconductive adhesive materials.
(FR) L'invention concerne un module (121), pourvu d'un stratifié (10) comprenant une pluralité de substrats stratifiés de résine isolante (11, 12, 13, 14), le stratifié (10) présentant une première surface principale (S1) et une seconde surface principale (S2) et présentant de premières zones (Z1) et de secondes zones (Z2) en vue en plan. Un premier motif conducteur (31) et un film protecteur (21) recouvrant le premier motif conducteur (31) sont formés dans la première région (Z1) de la première surface principale (S1). Des seconds motifs conducteurs (32G, 32S1) et des trous conduisant aux seconds motifs conducteurs (32G, 32S1) sont formés dans les secondes régions (Z2) du stratifié (10). Des matériaux adhésifs électroconducteurs (BG1, BG2, BS) sont enfoncés dans les trous, et des connecteurs (91, 92) sont connectés aux seconds motifs conducteurs par l'intermédiaire des matériaux adhésifs électroconducteurs.
(JA) モジュール(121)は、積層された複数の絶縁性樹脂基材(11,12,13,14)を含み、第1主面(S1)および第2主面(S2)を有し、平面視で第1領域(Z1)と第2領域(Z2)を有する積層体(10)を備える。第1主面(S1)の第1領域(Z1)には第1導体パターン(31)と、これを被覆する保護膜(21)が形成されている。積層体(10)の第2領域(Z2)には第2導体パターン(32G,32S1)と、これらにつながる孔が形成されている。これらの孔に導電性接合材(BG1,BG2,BS)が充填され、コネクタ(91,92)はこれら導電性接合材を介して第2導体パターンに接続される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)