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1. (WO2018037831) RESISTIVITY STANDARD SAMPLE MANUFACTURING METHOD AND EPITAXIAL WAFER RESISTIVITY MEASURING METHOD

Pub. No.:    WO/2018/037831    International Application No.:    PCT/JP2017/027384
Publication Date: Fri Mar 02 00:59:59 CET 2018 International Filing Date: Sat Jul 29 01:59:59 CEST 2017
IPC: H01L 21/66
G01N 27/00
G01N 27/04
G01N 27/22
Applicants: SHIN-ETSU HANDOTAI CO.,LTD.
信越半導体株式会社
Inventors: KUME Fumitaka
久米 史高
Title: RESISTIVITY STANDARD SAMPLE MANUFACTURING METHOD AND EPITAXIAL WAFER RESISTIVITY MEASURING METHOD
Abstract:
The present invention provides a resistivity standard sample manufacturing method comprising: a step of preparing a first conductivity-type silicon single-crystalline substrate; a step of measuring, using a thickness measuring device traceable to a national standard, the thickness of the silicon single-crystalline substrate; a step of fabricating an epitaxial wafer having a p-n junction by growing a second conductivity-type silicon epitaxial layer on the silicon single-crystalline substrate; a step of measuring the thickness of the epitaxial wafer using the thickness measuring device traceable to the national standard; a step of determining the thickness of the silicon epitaxial layer from the thicknesses of the epitaxial wafer and the silicon single-crystalline substrate; and a step of measuring the resistivity of the silicon epitaxial layer using a resistivity measuring device traceable to a resistivity standard substance. The resistivity standard sample manufacturing method enables the manufacture of a resistivity standard sample that is traceable to the resistivity standard substance, such as NIST.