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1. (WO2018037739) ETCHING METHOD AND METHOD FOR MANUFACTURING DRAM CAPACITOR
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Pub. No.: WO/2018/037739 International Application No.: PCT/JP2017/025097
Publication Date: 01.03.2018 International Filing Date: 10.07.2017
IPC:
H01L 21/3065 (2006.01) ,H01L 21/8242 (2006.01) ,H01L 27/108 (2006.01) ,H05H 1/46 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8242
Dynamic random access memory structures (DRAM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H
PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY- CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
1
Generating plasma; Handling plasma
24
Generating plasma
46
using applied electromagnetic fields, e.g. high frequency or microwave energy
Applicants:
東京エレクトロン株式会社 TOKYO ELECTRON LIMITED [JP/JP]; 東京都港区赤坂五丁目3番1号 3-1 Akasaka 5-chome, Minato-ku, Tokyo 1076325, JP
Inventors:
▲高▼橋 信博 TAKAHASHI Nobuhiro; JP
Agent:
高山 宏志 TAKAYAMA Hiroshi; JP
Priority Data:
2016-16193622.08.2016JP
Title (EN) ETCHING METHOD AND METHOD FOR MANUFACTURING DRAM CAPACITOR
(FR) PROCÉDÉ DE GRAVURE ET PROCÉDÉ DE FABRICATION DE CONDENSATEUR DE MÉMOIRE VIVE DYNAMIQUE
(JA) エッチング方法およびDRAMキャパシタの製造方法
Abstract:
(EN) A substrate to be treated, having a silicon portion, a silicon nitride film, and a silicon oxide film, is readied. A fluorine-containing gas and an inert gas are fed to the substrate to be treated in an excited state, and the silicon portion is selectively etched with respect to the silicon nitride film and the silicon oxide film.
(FR) Un substrat à traiter, ayant une partie en silicium, un film de nitrure de silicium et un film d'oxyde de silicium, est préparé. Un gaz contenant du fluor et un gaz inerte sont introduits dans le substrat à traiter dans un état excité, et la partie en silicium est sélectivement gravée par rapport au film de nitrure de silicium et au film d'oxyde de silicium.
(JA) シリコン部分と窒化シリコン膜と酸化シリコン膜を有する被処理基板を準備し、フッ素含有ガスと不活性ガスを励起した状態で前記被処理基板に供給して、シリコン部分を窒化シリコン膜および酸化シリコン膜に対して選択的にエッチングする。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)