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1. (WO2018037522) MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2018/037522 International Application No.: PCT/JP2016/074741
Publication Date: 01.03.2018 International Filing Date: 25.08.2016
IPC:
H01L 21/28 (2006.01) ,H01L 21/329 (2006.01) ,H01L 29/868 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328
Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
329
the devices comprising one or two electrodes, e.g. diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
868
PIN diodes
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
加地 考男 KACHI Takao; JP
吉浦 康博 YOSHIURA Yasuhiro; JP
Agent:
吉竹 英俊 YOSHITAKE Hidetoshi; JP
有田 貴弘 ARITA Takahiro; JP
Priority Data:
Title (EN) MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION POUR DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置の製造方法
Abstract:
(EN) The purpose of the present invention is to easily perform an electric specification test for guaranteeing the quality of a semiconductor device against pattern defects or damage of electrodes. This manufacturing method for a semiconductor device includes: performing, on a semiconductor device having a semiconductor substrate (1), a first semiconductor layer (2) formed on a first main surface (1a) side of the semiconductor substrate (1), and a first electrode film (5) formed on the first semiconductor layer (2) in contact therewith, a first etching from the top of the first electrode film (5) with a higher selectivity for the semiconductor material of the first semiconductor layer (2) than the material of the first electrode film (5); at least partially removing a region of the first semiconductor layer (2) below a pattern defect area (5a) or damaged area (5b) of the first electrode film (5); and forming an electrode film (8) on the pattern defect area (5a) or damaged area (5b) of the first electrode film (5).
(FR) Le but de la présente invention est de réaliser facilement un test de spécification électrique pour garantir la qualité d'un dispositif à semi-conducteur contre des défauts de motif ou des dommages d'électrodes. Ce procédé de fabrication d'un dispositif à semi-conducteur comprend : la réalisation, sur un dispositif à semi-conducteur ayant un substrat semi-conducteur (1), d'une première couche semi-conductrice (2) formée sur un coté d'une première surface principale (1a) du substrat semi-conducteur (1), et un premier film d'électrode (5) formé sur la première couche semi-conductrice (2) en contact avec celui-ci, une première gravure à partir de la partie supérieure du premier film d'électrode (5) avec une sélectivité supérieure pour le matériau semi-conducteur de la première couche semi-conductrice (2) au matériau du premier film d'électrode (5); éliminer au moins partiellement une région de la première couche semi-conductrice (2) en-dessous d'une zone de défaut de motif (5a) ou d'une zone endommagée (5b) du premier film d'électrode (5); et former un film d'électrode (8) sur la zone de défaut de motif (5a) ou la zone endommagée (5b) du premier film d'électrode (5).
(JA) 本発明は、電極のパターン欠陥又は欠損に対して半導体装置の品質を保証するための電気特定試験を、簡便に行うことを目的とする。本発明に係る半導体装置の製造方法は、半導体基板(1)と、半導体基板(1)の第1主面(1a)側に形成された第1半導体層(2)と、第1半導体層(2)上にこれに接して形成された第1電極膜(5)と、を有する半導体装置に、第1電極膜(5)上から、第1電極膜(5)の材料より第1半導体層(2)の半導体材料に対する選択比が高い第1エッチングを行い、第1半導体層(2)の、第1電極膜(5)のパターン欠陥箇所(5a)又は欠損箇所(5b)の下の領域を少なくとも部分的に除去し、第1電極膜(5)のパターン欠陥箇所(5a)又は欠損箇所(5b)に電極膜(8)を形成する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)