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1. (WO2018036319) SEMICONDUCTOR PACKAGING STRUCTURE AND MANUFACTURING METHOD

Pub. No.:    WO/2018/036319    International Application No.:    PCT/CN2017/093871
Publication Date: Fri Mar 02 00:59:59 CET 2018 International Filing Date: Sat Jul 22 01:59:59 CEST 2017
IPC: H01L 23/31
H01L 21/56
H01L 23/492
H01L 23/498
H01L 21/60
Applicants: GREAT TEAM BACKEND FOUNDRY (DONGGUAN), LTD.
杰群电子科技(东莞)有限公司
Inventors: CAO, Zhou
曹周
HSU, Cheng Chieh
徐振杰
Title: SEMICONDUCTOR PACKAGING STRUCTURE AND MANUFACTURING METHOD
Abstract:
Disclosed are a semiconductor packaging structure and a manufacturing method. The semiconductor packaging structure comprises a chip (1). The chip has a first surface and a second surface opposite the first surface, wherein the first surface and the second surface are both provided with an electrode. A solder paste (2) is coated on the surface of the electrode on the first surface, and a plastic packaging material (3) is coated on a position without the electrode arranged thereon on the first surface, with the outer surfaces of the solder paste and the plastic packaging material forming a packaging surface. The second surface is connected to an electrical connecting piece.