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1. (WO2018036027) METHOD FOR MANUFACTURING IPS TYPE ARRAY SUBSTRATE, AND IPS TYPE ARRAY SUBSTRATE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/036027 International Application No.: PCT/CN2016/110070
Publication Date: 01.03.2018 International Filing Date: 15.12.2016
IPC:
G02F 1/1343 (2006.01) ,H01L 27/12 (2006.01) ,H01L 21/77 (2017.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
1343
Electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号 No.9-2, Tangming Road, Guangming New District Shenzhen, Guangdong 518132, CN
Inventors:
周志超 ZHOU, Zhichao; CN
夏慧 XIA, Hui; CN
Agent:
深圳市德力知识产权代理事务所 COMIPS INTELLECTUAL PROPERTY OFFICE; 中国广东省深圳市 福田区上步中路深勘大厦15E Room 15E, Shenkan Building, Shangbu Zhong Road, Futian District Shenzhen, Guangdong 518028, CN
Priority Data:
201610711928.X23.08.2016CN
Title (EN) METHOD FOR MANUFACTURING IPS TYPE ARRAY SUBSTRATE, AND IPS TYPE ARRAY SUBSTRATE
(FR) PROCÉDÉ DE FABRICATION DE SUBSTRAT MATRICIEL DE TYPE IPS, ET SUBSTRAT MATRICIEL DE TYPE IPS
(ZH) IPS型阵列基板的制作方法及IPS型阵列基板
Abstract:
(EN) A method for manufacturing an IPS type array substrate, and an IPS type array substrate. The method for manufacturing an IPS type array substrate comprises: using a halftone mask (90) to prepare both a common electrode (21) and a pixel electrode (22) which are vertically staggered, and enabling the common electrode (21) to be located in a common electrode channel (151) of an insulating protective layer (15) and the pixel electrode (22) to be located on the upper surface of the insulating protective layer (15). Compared with a conventional IPS type array substrate, a vertical component of an electric field can be generated between the common electrode (21) and the pixel electrode (22) in the obtained IPS type array substrate. Therefore, liquid crystals above the pixel electrode in a liquid crystal panel can also be driven and utilized. The liquid crystals can rotate horizontally, and can also form a vertical tilt angle, thereby improving the utilization efficiency of the liquid crystals, and the light transmittance. Compared with an FFS type array substrate which also allows liquid crystals above a pixel electrode to be used, a photomask and a process can be saved, thereby reducing the production cost.
(FR) L'invention concerne un procédé de fabrication de substrat matriciel de type IPS, et un substrat matriciel de type IPS. Le procédé de fabrication d'un substrat matriciel de type IPS comprend les étapes suivantes : utiliser un masque en demi-teinte (90) pour préparer à la fois une électrode commune (21) et une électrode de pixel (22) qui sont décalées verticalement, et permettre à l'électrode commune (21) d'être située dans un canal d'électrode commune (151) d'une couche de protection isolante (15) et à l'électrode de pixel (22) d'être située sur la surface supérieure de la couche de protection isolante (15). Par rapport à un substrat matriciel de type IPS classique, une composante verticale d'un champ électrique peut être produite entre l'électrode commune (21) et l'électrode de pixel (22) dans le substrat matriciel de type IPS obtenu. Par conséquent, des cristaux liquides au-dessus de l'électrode de pixel dans un panneau à cristaux liquides peuvent également être pilotés et utilisés. Les cristaux liquides peuvent tourner horizontalement, et peuvent aussi former un angle d'inclinaison vertical, améliorant ainsi l'efficacité d'utilisation des cristaux liquides, et la transmittance de lumière. Par rapport à un substrat matriciel de type FFS qui permet également d'utiliser des cristaux liquides au-dessus d'une électrode de pixel, on peut économiser un photomasque et un processus, ce qui réduit le coût de production.
(ZH) 一种IPS型阵列基板的制作方法及IPS型阵列基板。IPS型阵列基板的制作方法,利用一半色调掩模板(90)同时制得纵向交错的公共电极(21)与像素电极(22),使公共电极(21)位于绝缘保护层(15)的公共电极沟道(151)内,像素电极(22)位于绝缘保护层(15)的上表面上,所得到的IPS型阵列基板与传统的IPS型阵列基板相比,公共电极(21)与像素电极(22)之间能够产生电场的纵向分量,所以在液晶面板内像素电极上方的液晶也能被驱动和利用,液晶不仅能水平转动,还能产生一定的纵向倾角,从而提高了液晶的利用效率和光线的透过率,与同样能利用像素电极上方液晶的FFS型阵列基板相比,可以节省一道光罩和制程,从而节约了生产成本。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)