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1. (WO2018035993) ARRAY SUBSTRATE AND LIQUID-CRYSTAL DISPLAY PANEL
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Pub. No.: WO/2018/035993 International Application No.: PCT/CN2016/106033
Publication Date: 01.03.2018 International Filing Date: 16.11.2016
IPC:
H01L 27/12 (2006.01) ,H01L 29/786 (2006.01) ,H01L 21/324 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
324
Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Applicants:
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD [CN/CN]; 中国湖北省武汉市 东湖开发区高新大道666号生物城C5栋 Building C5 Biolake of Optics Valley, No.666 Gaoxin Avenue, East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
谢应涛 XIE, Yingtao; CN
Agent:
深圳市威世博知识产权代理事务所(普通合伙) CHINA WISPRO INTELLECTUAL PROPERTY LLP.; 中国广东省深圳市 南山区高新区粤兴三道8号中国地质大学产学研基地中地大楼A806 Room A806, Zhongdi Building, China University of Geosciences Base, No.8 Yuexing 3rd Road, High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201610742652.126.08.2016CN
Title (EN) ARRAY SUBSTRATE AND LIQUID-CRYSTAL DISPLAY PANEL
(FR) SUBSTRAT DE MATRICE ET PANNEAU D’AFFICHAGE À CRISTAUX LIQUIDES
(ZH) 阵列基板及液晶显示面板
Abstract:
(EN) An array substrate and a liquid-crystal display panel, the array substrate comprising: after forming an oxide semiconductor material layer (14, 23, 24, 25), forming a passivation layer (17) or a gate insulating layer (13, 26) by annealing in compressed air with radio frequency irradiation. By means of the above technique, the difference between threshold voltages of a plurality of oxide thin film transistors can be adjusted, and a technical basis is further provided for reducing drift in the threshold voltages of oxide semiconductor TFTs, thereby realizing uniform display performance.
(FR) L’invention concerne un substrat de matrice et un panneau d’affichage à cristaux liquides, le substrat de matrice comprenant : après la formation d’une couche de matériau semi-conducteur d’oxyde (14, 23, 24, 25), la formation d’une couche de passivation (17) ou d’une couche isolante de grille (13, 26) par recuit dans l’air comprimé avec une irradiation à radiofréquence. Au moyen de la technique susmentionnée, la différence entre les tensions de seuil d’une pluralité de transistors à film mince d’oxyde peut être ajustée, et une base technique est en outre assurée pour la réduction de la dérive dans les tensions de seuil de TFT à semi-conducteurs d’oxyde, réalisant ainsi une performance d’affichage uniforme.
(ZH) 一种阵列基板及液晶显示面板,该阵列基板包括:在氧化物半导体材料层(14,23,24,25)形成后,在射频照射下、并在压缩空气中进行退火形成钝化层(17)或栅极绝缘层(13,26)。通过上述方式,能够调节多个氧化物薄膜晶体管的阈值电压之间的差异,并进而为减少氧化物半导体TFT阈值电压的漂移,实现均匀的显示效果提供技术基础。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)