Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018035902) METHOD FOR PREPARING LOW-TEMPERATURE POLYCRYSTALLINE SILICON ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY PANEL
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2018/035902 International Application No.: PCT/CN2016/099215
Publication Date: 01.03.2018 International Filing Date: 18.09.2016
IPC:
H01L 21/77 (2017.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD [CN/CN]; 中国湖北省武汉市 东湖开发区高新大道666号生物城C5栋 Building C5, Biolake of Optics Valley, No.666 Gaoxin Avenue Wuhan East Lake High-Tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
郝晓丹 HAO, Xiaodan; CN
殷婉婷 YIN, Wanting; CN
Agent:
深圳市威世博知识产权代理事务所(普通合伙) CHINA WISPRO INTELLECTUAL PROPERTY LLP.; 中国广东省深圳市 南山区高新区粤兴三道8号中国地质大学产学研基地中地大楼A806 Room A806 Zhongdi Building, China University of Geosciences Base, No.8 Yuexing 3rd Road High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201610717847.024.08.2016CN
Title (EN) METHOD FOR PREPARING LOW-TEMPERATURE POLYCRYSTALLINE SILICON ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY PANEL
(FR) PROCÉDÉ DE PRÉPARATION D'UN SUBSTRAT DE MATRICE DE SILICIUM POLYCRISTALLIN À BASSE TEMPÉRATURE, SUBSTRAT DE MATRICE ET PANNEAU D'AFFICHAGE
(ZH) 低温多晶硅阵列基板的制备方法、阵列基板以及显示面板
Abstract:
(EN) Disclosed is a method for preparing a low-temperature polycrystalline silicon array substrate. The method comprises: providing a substrate (200), and forming a buffer layer (202) on the substrate (200); forming a doped amorphous silicon thin film layer on the buffer layer (202) by means of the vapour deposition of a first mixed gas and an ion-doped gas; dehydrogenizing the amorphous silicon thin film layer by means of the vapour deposition of a second mixed gas; annealing the dehydrogenized amorphous silicon thin film layer so that doped ions are diffused so as to form a polycrystalline silicon layer (203); and patterning the polycrystalline silicon layer (203). This preparation method can effectively simplify the process for manufacturing a low-temperature polycrystalline silicon array substrate, reduce the investment in manufacturing equipment and reduce preparation costs. Further disclosed are an array substrate and a display panel.
(FR) La présente invention concerne un procédé de préparation d'un substrat de matrice de silicium polycristallin à basse température. Le procédé consiste : à fournir un substrat (200), et à former une couche tampon (202) sur le substrat (200) ; à former une couche de film mince de silicium amorphe dopé sur la couche tampon (202) au moyen du dépôt en phase vapeur d'un premier gaz mixte et d'un gaz dopé aux ions ; à déshydrogéner la couche de film mince de silicium amorphe au moyen du dépôt en phase vapeur d'un deuxième gaz mixte ; à recuire la couche de film mince de silicium amorphe déshydrogénée de telle sorte que les ions dopés sont diffusés de manière à former une couche de silicium polycristallin (203) ; et à effectuer un modèle sur la couche de silicium polycristallin (203). Ce procédé de préparation peut efficacement simplifier le processus de fabrication d'un substrat de matrice de silicium polycristallin à basse température, réduire l'investissement dans un équipement de fabrication et réduire les coûts de préparation. L'invention concerne en outre un substrat de matrice et un panneau d'affichage.
(ZH) 公开了一种低温多晶硅阵列基板的制备方法,包括:设置一基板(200),并在基板(200)上形成缓冲层(202);采用气象沉积第一混合气体以及掺杂离子气体的方式,在缓冲层(202)上形成掺杂的非晶硅薄膜层;采用气象沉积第二混合气体的方式,对非晶硅薄膜层进行去氢;对去氢后的非晶硅薄膜层进行退火处理,使参杂离子扩散,以形成多晶硅层(203);将多晶硅层(203)图案化。这种制备方法能够有效简化低温多晶硅阵列基板制造的工艺,减少制造设备的投入,降低制备成本。还公开了一种阵列基板和一种显示面板。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)