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1. (WO2018035361) QUANTUM COMPUTING METHODS AND DEVICES FOR MAJORANA QUBITS
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Pub. No.: WO/2018/035361 International Application No.: PCT/US2017/047418
Publication Date: 22.02.2018 International Filing Date: 17.08.2017
IPC:
G06N 99/00 (2010.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
99
Subject matter not provided for in other groups of this subclass
Applicants:
MICROSOFT TECHNOLOGY LICENSING, LLC [US/US]; One Microsoft Way Redmond, WA 98052, US
Inventors:
HASTINGS, Matthew; US
FREEDMAN, Michael; US
NAYAK, Chetan; US
LUTCHYN, Roman; US
KARZIG, Torsten; US
BONDERSON, Parsa; US
Agent:
BIBLE, Patrick M.; US
Priority Data:
15/634,98327.06.2017US
15/636,37628.06.2017US
15/636,45728.06.2017US
62/376,38617.08.2016US
62/378,21823.08.2016US
62/382,25331.08.2016US
62/385,24508.09.2016US
Title (EN) QUANTUM COMPUTING METHODS AND DEVICES FOR MAJORANA QUBITS
(FR) PROCÉDÉS ET DISPOSITIFS DE CALCUL QUANTIQUE POUR BITS QUANTIQUES DE MAJORANA
Abstract:
(EN) Among the embodiments disclosed herein are example methods for generating all Clifford gates for a system of Majorana Tetron qubits (quasiparticle poisoning protected) given the ability to perform certain 4 Majorana zero mode measurements. Also disclosed herein are example designs for scalable quantum computing architectures that enable the methods for generating the Clifford gates, as well as other operations on the states of MZMs. These designs are configured in such a way as to allow the generation of all the Clifford gates with topological protection and non-Clifford gates (e.g. a π/ 8-phase gate) without topological protection, thereby producing a computationally universal gate set. Several possible realizations of these architectures are disclosed.
(FR) L'invention concerne, parmi les modes de réalisation décrits, des procédés illustratifs permettant de générer toutes les portes de Clifford pour un système de bits quantiques de Majorana Tetron (à protection contre l'empoisonnement par des quasi-particules) pouvant effectuer certaines mesures de modes zéro de 4 Majorana. L'invention concerne également des conceptions illustratives pour des architectures de calcul quantique évolutives qui autorisent des procédés de génération des portes de Clifford, ainsi que d'autres opérations sur les états de MZM. Ces conceptions sont configurées de manière à permettre la génération de toutes les portes de Clifford avec protection topologique et portes de non-Clifford (par exemple une porte en phase π/8) sans protection topologique, ce qui permet de produire un ensemble de portes à calcul universel. L'invention concerne par ailleurs plusieurs réalisations possibles de ces architectures.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)