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1. (WO2018034770) DENSITY-OPTIMIZED MODULE-LEVEL INDUCTOR GROUND STRUCTURE
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Pub. No.: WO/2018/034770 International Application No.: PCT/US2017/042555
Publication Date: 22.02.2018 International Filing Date: 18.07.2017
Chapter 2 Demand Filed: 05.06.2018
IPC:
H05K 1/02 (2006.01) ,H01L 49/02 (2006.01) ,H01L 23/522 (2006.01) ,H01L 23/552 (2006.01) ,H01L 23/64 (2006.01) ,H01L 23/00 (2006.01) ,H05K 3/06 (2006.01) ,H05K 1/14 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
49
Solid state devices not provided for in groups H01L27/-H01L47/99; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
02
Thin-film or thick-film devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
552
Protection against radiation, e.g. light
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
64
Impedance arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
02
in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
06
the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
14
Structural association of two or more printed circuits
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
BERDY, David Francis; US
YUN, Changhan Hobie; US
MUDAKATTE, Niranjan Sunil; US
VELEZ, Mario Francisco; US
ZUO, Chengjie; US
KIM, Jonghae; US
Agent:
LENKIN, Alan M.; US
LUTZ, Joseph; US
PARTOW-NAVID, Puya; US
FASHU-KANU, Alvin V.; US
Priority Data:
15/239,75117.08.2016US
Title (EN) DENSITY-OPTIMIZED MODULE-LEVEL INDUCTOR GROUND STRUCTURE
(FR) STRUCTURE DE MISE À LA MASSE D'INDUCTEUR AU NIVEAU DU MODULE OPTIMISÉE EN DENSITÉ
Abstract:
(EN) An integrated circuit (IC) device (300) may include a first substrate (310) having an inductor ground plane (320) in a conductive layer of the first substrate. The integrated circuit may also include a first inductor (340) in a passive device layer (332) of a second substrate (330) that is supported by the first substrate. A shape of the inductor ground plane may substantially correspond to a silhouette of the first inductor.
(FR) Selon l'invention, un dispositif de circuit intégré (CI) peut comprendre un premier substrat (310) doté d'un plan de masse d'inducteur (320) dans une couche conductrice du premier substrat. Le CI peut également comprendre un premier inducteur (340) dans une couche de dispositif passif (332) d'un second substrat (330) qui est soutenu par le premier substrat. Une forme du plan de masse d'inducteur peut sensiblement correspondre à une silhouette du premier inducteur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)