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1. (WO2018034756) UTILIZATION OF BACKSIDE SILICIDATION TO FORM DUAL SIDE CONTACTED CAPACITOR
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Pub. No.: WO/2018/034756 International Application No.: PCT/US2017/042213
Publication Date: 22.02.2018 International Filing Date: 14.07.2017
Chapter 2 Demand Filed: 16.05.2018
IPC:
H01L 29/94 (2006.01) ,H01L 27/12 (2006.01) ,H01L 29/66 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
92
Capacitors with potential-jump barrier or surface barrier
94
Metal-insulator-semiconductors, e.g. MOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
GOKTEPELI, Sinan; US
KOLEV, Plamen Vassilev; US
STUBER, Michael Andrew; US
HAMMOND, Richard; GB
GU, Shiqun; US
FANELLI, Stephen ALan; US
Agent:
LENKIN, Alan M.; US
LUTZ, Joseph; US
PARTOW-NAVID, Puya; US
FASHU-KANU, Alvin V.; US
Priority Data:
15/240,95218.08.2016US
Title (EN) UTILIZATION OF BACKSIDE SILICIDATION TO FORM DUAL SIDE CONTACTED CAPACITOR
(FR) UTILISATION DE SILICIURATION DE FACE ARRIÈRE POUR FORMER UN CONDENSATEUR À CONTACT LATÉRAL DOUBLE
Abstract:
(EN) An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
(FR) Une structure de circuit intégré peut comprendre un condensateur ayant une couche semi-conductrice en tant que première plaque et une couche de grille en tant que seconde plaque. Une couche diélectrique de condensateur peut séparer la première plaque et la seconde plaque. Une métallisation de face arrière peut être couplée à la première plaque du condensateur. Une métallisation de face avant peut être couplée à la seconde plaque du condensateur. La métallisation de face avant peut être disposée de manière distale par rapport à la métallisation de face arrière.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)