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1. (WO2018033916) HETEROSTRUCTURE SYSTEM AND METHOD OF FABRICATING THE SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/033916 International Application No.: PCT/IL2017/050907
Publication Date: 22.02.2018 International Filing Date: 16.08.2017
IPC:
H01L 21/70 (2006.01) ,H01L 21/762 (2006.01) ,H01L 21/02 (2006.01) ,H01L 21/20 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
Applicants: RAMOT AT TEL-AVIV UNIVERSITY LTD.[IL/IL]; P.O. Box 39296 6139201 Tel-Aviv, IL
Inventors: DAGAN, Yoram; IL
MARKOVICH, Gil; IL
RON, Alon; IL
HEVRONI, Amir; IL
Agent: EHRLICH, Gal; IL
WATERMAN, Hadassa; IL
MELNICK, Geoffrey, L.; IL
Priority Data:
62/375,50816.08.2016US
Title (EN) HETEROSTRUCTURE SYSTEM AND METHOD OF FABRICATING THE SAME
(FR) SYSTÈME À HÉTÉRO-STRUCTURE ET PROCÉDÉ DE FABRICATION ASSOCIÉ
Abstract:
(EN) A method of fabricating a heterostructure system, comprises epitaxially growing a crystalline layer of a first substance on a crystalline base layer by surface catalysis in a solution, wherein the growth is self-terminated once a monolayer of the substance is formed on the base layer.
(FR) Un procédé de fabrication d'un système à hétéro-structure comprend la croissance épitaxiale d'une couche cristalline d'une première substance sur une couche de base cristalline par catalyse de surface dans une solution, la croissance étant auto-terminée une fois qu'une monocouche de la substance est formée sur la couche de base.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)