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1. (WO2018032960) ARRAY SUBSTRATE AND DISPLAY PANEL

Pub. No.:    WO/2018/032960    International Application No.:    PCT/CN2017/095198
Publication Date: Fri Feb 23 00:59:59 CET 2018 International Filing Date: Tue Aug 01 01:59:59 CEST 2017
IPC: G09G 3/36
G11C 19/28
Applicants: BOE TECHNOLOGY GROUP CO., LTD.
京东方科技集团股份有限公司
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
北京京东方显示技术有限公司
Inventors: WANG, Zheng
王峥
Title: ARRAY SUBSTRATE AND DISPLAY PANEL
Abstract:
An array substrate and a display panel, the array substrate comprising shift registers (Gn) corresponding to each gate line. A transistor, in shift registers of various stages, connected with a corresponding-stage gate line (gate n) and next-stage gate line (gate n+1) is a first transistor (M9); a signal line, among a plurality of signal lines connected with the shift registers (Gn), connected with the first transistor (M9), is a first signal line (VSS); the first transistor (M9) and the signal line connected with the first transistor (M9) are arranged in a display area (10). The width of a frame area (20) can be reduced without complicating wiring layout design of the array substrate.