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1. (WO2018031528) THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/031528 International Application No.: PCT/US2017/045864
Publication Date: 15.02.2018 International Filing Date: 08.08.2017
IPC:
H01L 29/16 (2006.01) ,H01L 29/161 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
16
including, apart from doping materials or other impurities, only elements of the fourth group of the Periodic System in uncombined form
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
16
including, apart from doping materials or other impurities, only elements of the fourth group of the Periodic System in uncombined form
161
including two or more of the elements provided for in group H01L29/1688
Applicants: SMITH, Jeffrey[US/US]; US (US)
DEVILLIERS, Anton, J.[US/US]; US (US)
MOHANTY, Nihar[IN/US]; US (US)
KAL, Subhadeep[IN/US]; US (US)
TAPILY, Kandarara[ML/US]; US (US)
TOKYO ELECTRON LIMITED[JP/JP]; Akasaka Biz Tower 3-1, Akasaka 5-chome Minato-ku, 107-6325, JP
Inventors: SMITH, Jeffrey; US
DEVILLIERS, Anton, J.; US
MOHANTY, Nihar; US
KAL, Subhadeep; US
TAPILY, Kandarara; US
Agent: SIGNORE, Philippe, J.C.; US
MASON, J., Derek; US
Priority Data:
62/372,10608.08.2016US
Title (EN) THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
(FR) DISPOSITIF À SEMI-CONDUCTEUR TRIDIMENSIONNEL ET PROCÉDÉ DE FABRICATION
Abstract:
(EN) A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.
(FR) L'invention porte sur un dispositif à semi-conducteur comprenant un substrat et une région de grille d'un transistor à effet de champ formée sur le substrat. La région de grille comprend des nanofils empilés verticalement ayant des axes longitudinaux qui s'étendent parallèlement à une surface de travail du substrat. Un empilement donné de nanofils empilés verticalement comprend au moins deux nanofils alignés verticalement dans lesquels un nanofil de type p et un nanofil de type n sont spatialement séparés l'un de l'autre verticalement. Le dispositif à semi-conducteur comprend en outre une structure de connexion en forme de gradin formée à l'intérieur de la région de grille qui connecte électriquement chaque nanofil à des emplacements au-dessus de la région de grille. Une première électrode de grille présente un profil en forme de gradin et se connecte à un nanofil de premier niveau.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)