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1. (WO2018031527) SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS COMPRISING A SUPERLATTICE AND ASSOCIATED METHODS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/031527 International Application No.: PCT/US2017/045863
Publication Date: 15.02.2018 International Filing Date: 08.08.2017
IPC:
H01L 29/88 (2006.01) ,H01L 21/329 (2006.01) ,H01L 29/15 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
88
Tunnel-effect diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328
Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
329
the devices comprising one or two electrodes, e.g. diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
15
Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
Applicants: ATOMERA INCORPORATED[US/US]; 750 University Avenue Suite 280 Los Gatos, California 95032, US
Inventors: MEARS, Robert J.; US
TAKEUCHI, Hideki; US
HYTHA, Marek; US
Agent: REGAN, Christopher F.; US
WARTHER, Richard K.; US
WOODSON, II, John F.; US
TAYLOR, Michael W.; US
ABID, Jack G.; US
CARUS, David S.; US
MCKINNEY, Matthew G.; US
Priority Data:
15/670,26607.08.2017US
15/670,27407.08.2017US
62/371,97108.08.2016US
Title (EN) SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS COMPRISING A SUPERLATTICE AND ASSOCIATED METHODS
(FR) DISPOSITIF À SEMI-CONDUCTEUR COMPRENANT UNE STRUCTURE DE DIODE À EFFET TUNNEL RÉSONNANT AVEC DES COUCHES DE COMMANDE DE LIBRE PARCOURS MOYEN DE L'ÉLECTRON COMPRENANT UN SUPER-RÉSEAU ET PROCÉDÉS ASSOCIÉS
Abstract:
(EN) A semiconductor device includes at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD includes a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD further includes a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer is on the third barrier layer, a fourth barrier layer is on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer is on the fourth barrier layer.
(FR) Un dispositif à semi-conducteur comprend au moins une diode à effet tunnel résonnant à double barrière (DBRTD). La ou les DBRTD comprennent une première couche semi-conductrice dopée, et une première couche barrière sur la première couche semi-conductrice dopée et comprenant un super-réseau. La DBRTD comprend en outre une première couche semi-conductrice intrinsèque sur la première couche barrière, une deuxième couche barrière sur la première couche semi-conductrice intrinsèque et comprenant également le super-réseau, une deuxième couche semi-conductrice intrinsèque sur la deuxième couche barrière, une troisième couche barrière sur la deuxième couche semi-conductrice intrinsèque et comprenant également le super-réseau. Une troisième couche semi-conductrice intrinsèque est située sur la troisième couche barrière, une quatrième couche barrière se trouve sur la troisième couche semi-conductrice intrinsèque et comprenant également le super-réseau, une seconde couche semi-conductrice dopée est située sur la quatrième couche barrière.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)