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1. (WO2018031154) CHIP ON CHIP (COC) PACKAGE WITH INTERPOSER
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Pub. No.: WO/2018/031154 International Application No.: PCT/US2017/041206
Publication Date: 15.02.2018 International Filing Date: 07.07.2017
IPC:
H01L 25/07 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
DOMINGUEZ, Juan E.; US
YIM, Myung Jin; US
Agent:
MOORE, Michael S.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BRASK, Justin K.; US
COFIELD, Michael A.; US
COWGER, Graciela G.; US
DANSKIN, Timothy A.; US
FORD, Stephen S.; US
GARTHWAITE, Martin S.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
PARKER, Wesley E.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
Priority Data:
15/231,51008.08.2016US
Title (EN) CHIP ON CHIP (COC) PACKAGE WITH INTERPOSER
(FR) BOÎTIER DE PUCE SUR PUCE (COC) AYANT UN ÉLÉMENT D'INTERPOSITION
Abstract:
(EN) Embodiments herein may relate to a chip-on-chip (CoC) package that includes a first integrated circuit (IC) die with an active side coupled with an active side of a second IC die. The CoC package may further include a substrate with a conductive metal post extending from a side of the substrate. An interposer may be positioned between, and coupled with the conductive metal post and the active side of the first IC die such that an area between an inactive side of the second IC die and the substrate is free of the interposer. Other embodiments may be described and/or claimed.
(FR) La présente invention se rapporte, dans des modes de réalisation, à un boîtier de puce sur puce (CoC pour Chip-on-Chip) qui comprend une première puce de circuit intégré (IC pour Integrated Circuit) ayant un côté actif couplé à un côté actif d'une seconde puce de circuit intégré. Le boîtier de puce sur puce peut en outre comprendre un substrat ayant un montant métallique conducteur s'étendant à partir d'un côté du substrat. Un élément d'interposition peut être positionné entre le montant métallique conducteur et le côté actif de la première puce de circuit intégré, et couplé à ces derniers, de telle sorte qu'une zone entre un côté inactif de la seconde puce de circuit intégré et le substrat soit dépourvue de l'élément d'interposition. D'autres modes de réalisation peuvent être décrits et/ou revendiqués.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)