Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018029965) SEMICONDUCTOR INTEGRATED CIRCUIT
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/029965 International Application No.: PCT/JP2017/021289
Publication Date: 15.02.2018 International Filing Date: 08.06.2017
IPC:
H01L 27/088 (2006.01) ,H01L 21/8234 (2006.01) ,H01L 27/146 (2006.01) ,H04N 5/374 (2011.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
374
Addressed sensors, e.g. MOS or CMOS sensors
Applicants:
ソニー株式会社 SONY CORPORATION [JP/JP]; 東京都港区港南1丁目7番1号 1-7-1 Konan, Minato-ku, Tokyo 1080075, JP
Inventors:
荻田 知治 OGITA, Tomoharu; JP
Agent:
丸島 敏一 MARUSHIMA, Toshikazu; JP
Priority Data:
2016-15708010.08.2016JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT
(FR) CIRCUIT INTÉGRÉ À SEMI-CONDUCTEUR
(JA) 半導体集積回路
Abstract:
(EN) The present invention suppresses a leak current in a semiconductor integrated circuit wherein a plurality of semiconductor substrates are laminated via a silicon through via. One of a P-type impurity and an N-type impurity is injected into a silicon substrate up to a predetermined concentration. In a plurality of channels, the other one of the P-type impurity and the N-type impurity is injected into one silicon substrate surface up to a concentration higher than the predetermined concentration. Electrodes are formed in the channels, respectively. In a well layer, the impurity same as that injected into the silicon substrate is injected between the other silicon substrate surface and the channels up to a concentration higher than the predetermined concentration.
(FR) La présente invention permet de supprimer un courant de fuite dans un circuit intégré à semi-conducteur dans lequel une pluralité de substrats semi-conducteurs sont stratifiés par le biais d'un trou d'interconnexion traversant le silicium. Une impureté de type P ou une impureté de type N est injectée dans un substrat de silicium à une concentration prédéterminée. Dans une pluralité de canaux, l'autre impureté parmi l'impureté de type P ou l'impureté de type N est injectée dans une surface de substrat de silicium à une concentration supérieure à la concentration prédéterminée. Des électrodes sont formées dans les canaux, respectivement. Dans une couche de puits, l'impureté identique à l'impureté injectée dans le substrat de silicium est injectée entre l'autre surface du substrat de silicium et les canaux à une concentration supérieure à la concentration prédéterminée.
(JA) シリコン貫通ビアを介して複数の半導体基板が積層された半導体集積回路において、リーク電流を抑制する。 シリコン基板には、P型不純物およびN型不純物のうち一方が所定濃度まで注入される。複数のチャネルには、シリコン基板の一方の面においてP型不純物およびN型不純物のうち他方が所定濃度より多く注入される。電極は、複数のチャネルのそれぞれに形成される。ウェル層には、シリコン基板の他方の面と前記複数のチャネルとの間においてシリコン基板と同一の不純物が所定濃度より多く注入される。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)