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Pub. No.: WO/2018/029801 International Application No.: PCT/JP2016/073549
Publication Date: 15.02.2018 International Filing Date: 10.08.2016
H01L 25/07 (2006.01) ,H01L 23/12 (2006.01) ,H01L 25/18 (2006.01)
Applicants: MITSUBISHI ELECTRIC CORPORATION[JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors: HAYASHIDA, Yukimasa; JP
DATE, Ryutaro; JP
Agent: TAKADA, Mamoru; JP
Priority Data:
(JA) 半導体装置
Abstract: front page image
(EN) A first and a second circuit pattern (5, 6) are provided on an insulated substrate (1). A first and a second semiconductor chip (7, 8) are provided on the first circuit pattern (5). A relay circuit pattern (10) is provided between the first semiconductor chip (7) and the second semiconductor chip (8) on the insulated substrate (1). A wire (11) is connected in continuation to the first semiconductor chip (7), the relay circuit pattern (10), the second semiconductor chip (8), and the second circuit pattern (6) arranged in sequence in one direction.
(FR) Un premier et un second motif de circuit (5, 6) sont disposés sur un substrat isolé (1). Une première et une seconde puce semi-conductrice (7, 8) sont disposées sur le premier motif de circuit (5). Un motif de circuit de relais (10) est disposé entre la première puce semi-conductrice (7) et la seconde puce semi-conductrice (8) sur le substrat isolé (1). Un fil (11) est connecté en continuation à la première puce semi-conductrice (7), au motif de circuit relais (10), à la seconde puce semi-conductrice (8), et au second motif de circuit (6) agencés en séquence dans une direction.
(JA) 絶縁基板(1)上に第1及び第2の回路パターン(5,6)が設けられている。第1の回路パターン(5)上に第1及び第2の半導体チップ(7,8)が設けられている。絶縁基板(1)上において、第1の半導体チップ(7)と第2の半導体チップ(8)の間に中継回路パターン(10)が設けられている。一方向に順に並べられた第1の半導体チップ(7)、中継回路パターン(10)、第2の半導体チップ(8)及び第2の回路パターン(6)にワイヤ(11)が連続して接続されている。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)