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1. (WO2018029556) AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/029556 International Application No.: PCT/IB2017/054419
Publication Date: 15.02.2018 International Filing Date: 21.07.2017
IPC:
H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION[US/US]; New Orchard Road Armonk, New York 10504, US
IBM UNITED KINGDOM LIMITED[GB/GB]; PO Box 41, North Harbour Portsmouth Hampshire PO6 3AU, GB (MG)
IBM (CHINA) INVESTMENT COMPANY LIMITED[CN/CN]; 25/F, Pangu Plaza No.27, Central North 4th Ring Road Chaoyang District Beijing 100101, CN (MG)
Inventors: NGUYEN, Son, Van; US
YAMASHITA, Tenko; US
CHENG, Kangguo; US
HAIGH JR, Thomas, Jasper; US
PARK, Chanro; US
LINIGER, Eric; US
LI, Juntao; US
MEHTA, Sanjay; US
Agent: FOURNIER, Kevin; GB
Priority Data:
15/232,34109.08.2016US
Title (EN) AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES
(FR) FORMATION D'ESPACEURS D'ENTREFER POUR DISPOSITIFS À SEMI-CONDUCTEURS À ÉCHELLE NANOMÉTRIQUE
Abstract:
(EN) Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.
(FR) L'invention porte sur des dispositifs à semi-conducteurs ayant des espaceurs d'entrefer qui sont formés en tant que partie de couches BEOL ou MOL des dispositifs à semi-conducteurs, ainsi que sur des procédés de fabrication de tels espaceurs d'entrefer. Par exemple, un procédé consiste à former une première structure métallique et une seconde structure métallique sur un substrat, les première et seconde structures métalliques étant disposées adjacentes l'une à l'autre avec un matériau isolant disposé entre les première et seconde structures métalliques. Le matériau isolant est gravé pour former un espace entre les première et seconde structures métalliques. Une couche de matériau diélectrique est déposée sur les première et seconde structures métalliques à l'aide d'un procédé de dépôt par pincement pour former un entrefer dans l'espace entre les première et seconde structures métalliques, une portion de l'entrefer s'étendant au-dessus d'une surface supérieure d'au moins une de la première structure métallique et de la seconde structure métallique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)