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1. (WO2018025580) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.:    WO/2018/025580    International Application No.:    PCT/JP2017/024918
Publication Date: 08.02.2018 International Filing Date: 07.07.2017
IPC:
H01L 21/82 (2006.01), H01L 21/822 (2006.01), H01L 21/8234 (2006.01), H01L 21/8238 (2006.01), H01L 27/04 (2006.01), H01L 27/06 (2006.01), H01L 27/092 (2006.01), H01L 29/06 (2006.01)
Applicants: SOCIONEXT INC. [JP/JP]; 2-10-23 Shin-Yokohama, Kohoku-Ku, Yokohama-shi, Kanagawa 2220033 (JP)
Inventors: SHIMBO Hiroyuki; (--)
Agent: MAEDA & PARTNERS; Shin-Daibiru Bldg. 23F, 2-1, Dojimahama 1-chome, Kita-ku, Osaka-shi, Osaka 5300004 (JP)
Priority Data:
2016-151125 01.08.2016 JP
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
(FR) DISPOSITIF DE CIRCUIT INTÉGRÉ À SEMI-CONDUCTEUR
(JA) 半導体集積回路装置
Abstract: front page image
(EN)Provided is a semiconductor integrated circuit device, using a nanowire FET, that has a layout configuration effective in facilitating easy manufacturing. A standard cell (C2) having no logical function is disposed adjacent to a standard cell (C1) having a logical function. The standard cell (C1) has nanowire FETs (P11, P12, N11, N12) having nanowires (11, 12, 13, 14) and pads (21, 22, 23, 24, 25, 26). The standard cell (C2) has dummy pads (51, 52, 53, 54) that are pads having no contribution to a logical function of the circuit.
(FR)L'invention porte sur un dispositif de circuit intégré à semi-conducteur, utilisant un transistor à effet de champ à nanofil, qui a une configuration de disposition efficace pour faciliter la fabrication. Une cellule standard (C2) n'ayant aucune fonction logique est disposée adjacente à une cellule standard (C1) ayant une fonction logique. La cellule standard (C1) comporte des transistors à effet de champ à nanofil (P11, P12, N11, N12) ayant des nanofils (11, 12, 13, 14) et des plages de connexion (21, 22, 23, 24 25, 26). La cellule standard (C2) comporte des plages de connexion factices (51, 52, 53, 54) qui sont des plages de connexion n'ayant pas de contribution à une fonction logique du circuit.
(JA)ナノワイヤFETを用いた半導体集積回路装置について、製造の容易化に有効なレイアウト構成を提供する。論理機能を有するスタンダードセル(C1)に隣接して、論理機能を有しないスタンダードセル(C2)が配置されている。スタンダードセル(C1)は、ナノワイヤ(11,12,13,14)およびパッド(21,22,23,24,25,26)を有するナノワイヤFET(P11,P12,N11,N12)を備えており、スタンダードセル(C2)は、回路の論理機能に寄与しないパッドであるダミーパッド(51,52,53,54)を備えている。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)