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1. (WO2018024797) SEQUENCE VERIFICATION
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Pub. No.: WO/2018/024797 International Application No.: PCT/EP2017/069578
Publication Date: 08.02.2018 International Filing Date: 02.08.2017
IPC:
G06F 21/72 (2013.01) ,G06F 21/55 (2013.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70
Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71
to assure secure computing or processing of information
72
in cryptographic circuits
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
50
Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
55
Detecting local intrusion or implementing counter-measures
Applicants:
NAGRAVISION SA [CH/CH]; 22-24 Route de Geneve 1033 Cheseaux-sur-Lausanne, CH
Inventors:
MACCHETTI, Marco; CH
FISCHER, Nicolas; CH
PERRINE, Jerome; CH
Agent:
KORENBERG, Alexander Tal; GB
Priority Data:
16182872.804.08.2016EP
Title (EN) SEQUENCE VERIFICATION
(FR) VÉRIFICATION DE SÉQUENCES
Abstract:
(EN) A method of monitoring execution in an execution environment of an operation, for example a cryptographic operation, comprising a sequence of instructions, is disclosed. Instructions sent in the sequence from a main processor to one or more auxiliary processors, for example cryptographic processors, to execute the operation are monitored and the sequence of instructions is verified using verification information. The method comprises enabling output from the execution environment of a result of the operation in response to a successful verification of the sequence, or generating a verification failure signal in response to a failed verification of the sequence.
(FR) L'invention concerne un procédé permettant de surveiller l'exécution dans un environnement d'exécution d'une opération, par exemple une opération cryptographique, comprenant une séquence d'instructions. Les instructions envoyées dans la séquence d'un processeur principal à un ou plusieurs processeurs auxiliaires, par exemple des processeurs cryptographiques, afin d'exécuter l'opération sont surveillées, puis la séquence d'instructions est vérifiée à l'aide d'informations de vérification. Le procédé consiste à permettre la génération, à partir de l'environnement d'exécution, d'un résultat de l'opération en réponse à une vérification réussie de la séquence, ou à générer un signal de défaut de vérification en réponse à un échec de vérification de la séquence.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)