Search International and National Patent Collections

1. (WO2018022382) VARIABLE PAGE SIZE ARCHITECTURE

Pub. No.:    WO/2018/022382    International Application No.:    PCT/US2017/042895
Publication Date: Fri Feb 02 00:59:59 CET 2018 International Filing Date: Thu Jul 20 01:59:59 CEST 2017
IPC: G06F 12/02
G06F 13/16
Applicants: MICRON TECHNOLOGY, INC.
Inventors: VILLA, Corrado
Title: VARIABLE PAGE SIZE ARCHITECTURE
Abstract:
Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.