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1. (WO2018022244) STANDARD CELL CIRCUITS EMPLOYING HIGH ASPECT RATIO VOLTAGE RAILS FOR REDUCED RESISTANCE
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Pub. No.: WO/2018/022244 International Application No.: PCT/US2017/039870
Publication Date: 01.02.2018 International Filing Date: 29.06.2017
Chapter 2 Demand Filed: 16.04.2018
IPC:
H01L 27/02 (2006.01) ,G06F 17/50 (2006.01) ,H01L 23/528 (2006.01) ,H01L 27/118 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
50
Computer-aided design
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528
Layout of the interconnection structure
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
118
Masterslice integrated circuits
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
XU, Jeffrey, Junhao; US
BADAROGLU, Mustafa; US
YANG, Da; US
CHIDAMBARAM, Periannan; US
Agent:
AYCOCK, Bradley, R.; US
DAVENPORT, Taylor, M.; US
Priority Data:
15/634,03927.06.2017US
62/367,23027.07.2016US
Title (EN) STANDARD CELL CIRCUITS EMPLOYING HIGH ASPECT RATIO VOLTAGE RAILS FOR REDUCED RESISTANCE
(FR) CIRCUITS INTÉGRÉS PRÉCARACTÉRISÉS UTILISANT DES RAILS DE TENSION À FACTEUR DE FORME ÉLEVÉ POUR RÉDUIRE LA RÉSISTANCE
Abstract:
(EN) Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed.In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage.A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail.A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0.The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.
(FR) L'invention concerne des circuits intégrés précaractérisés utilisant des rails de tension à facteur de forme élevé pour réduire la résistance. Dans un aspect, l'invention concerne un circuit intégré précaractérisé qui utilise : un premier rail de tension à facteur de forme élevé, configuré pour recevoir une première tension d'alimentation ; un second rail de tension à facteur de forme élevé, qui est placé de façon sensiblement parallèle au premier rail de tension à facteur de forme élevé. Un différentiel de tension entre le premier et le second rail de tension à facteur de forme élevé, est utilisé pour alimenter un dispositif de circuit dans le circuit intégré précaractérisé. Les premier et second rails de tension à facteur de forme élevé comportent chacun un rapport hauteur-largeur supérieur à 1. La hauteur respective de chaque premier et second rail de tension respectif à facteur de forme élevé est supérieure à chaque largeur respective. L'utilisation du premier et du second rail de tension à facteur de forme élevé permet à chaque rail de présenter une section transversale qui limite la résistance ainsi que la chute de tension ohmique correspondante.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)