WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2018022175) TECHNIQUES TO ALLOCATE REGIONS OF A MULTI LEVEL, MULTITECHNOLOGY SYSTEM MEMORY TO APPROPRIATE MEMORY ACCESS INITIATORS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.:    WO/2018/022175    International Application No.:    PCT/US2017/033378
Publication Date: 01.02.2018 International Filing Date: 18.05.2017
IPC:
G06F 13/16 (2006.01)
Applicants: INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054 (US)
Inventors: LIU, Min; (US).
LUO, Zhenlin; (CN).
VERGIS, George; (US).
NACHIMUTHU, Murugasamy K.; (US).
KUMAR, Mohan J.; (US).
ZWISLER, Ross E.; (US)
Agent: O'ROURKE, Robert B.; (US)
Priority Data:
15/224,134 29.07.2016 US
Title (EN) TECHNIQUES TO ALLOCATE REGIONS OF A MULTI LEVEL, MULTITECHNOLOGY SYSTEM MEMORY TO APPROPRIATE MEMORY ACCESS INITIATORS
(FR) TECHNIQUES PERMETTANT D'ATTRIBUER DES RÉGIONS D'UNE MÉMOIRE SYSTÈME MULTITECHNOLOGIE À PLUSIEURS NIVEAUX À DES DÉCLENCHEURS D'ACCÈS MÉMOIRE APPROPRIÉS
Abstract: front page image
(EN)A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with a respective region of the system memory having an appropriate latency and/or bandwidth.
(FR)L'invention concerne un procédé. Ce procédé consiste à reconnaître différents temps d'attente et/ou largeurs de bande entre différents niveaux d'une mémoire système et différents demandeurs d'accès mémoire d'un système informatique. La mémoire système comprend les différents niveaux et différentes technologies. Le procédé consiste également à attribuer à chacun des demandeurs d'accès mémoire une région respective de la mémoire système ayant une latence et/ou une largeur de bande appropriées.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)