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1. (WO2018020864) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/020864 International Application No.: PCT/JP2017/021633
Publication Date: 01.02.2018 International Filing Date: 12.06.2017
IPC:
H01L 21/56 (2006.01) ,H01L 23/28 (2006.01) ,H01L 23/50 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
50
for integrated circuit devices
Applicants:
株式会社東海理化電機製作所 KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO [JP/JP]; 愛知県丹羽郡大口町豊田三丁目260番地 260, Toyota 3-chome, Ohguchi-cho, Niwa-gun, Aichi 4800195, JP
Inventors:
原 貴之 HARA, Takayuki; JP
Agent:
特許業務法人平田国際特許事務所 HIRATA & PARTNERS; 東京都千代田区二番町4番地3 二番町カシュービル6階 6th Floor, Niban-cho Cashew Building, 4-3, Niban-cho, Chiyoda-ku, Tokyo 1020084, JP
Priority Data:
2016-14808128.07.2016JP
Title (EN) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ PERMETTANT DE FABRIQUER UN DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置の製造方法
Abstract:
(EN) According to the present invention, a semiconductor device 1 is manufactured by: preparing a lead frame 2 in which a plurality of circuit pattern forming regions 20 are formed side by side; attaching electronic components to the circuit pattern forming regions 20 to form an electronic circuit unit 3; forming a first sealed body 4 with a sealing resin such that the electronic circuit unit 3 is covered and a plurality of outer leads are exposed; cutting off a portion of a tie bar 23 connecting the plurality of outer leads to thereby form anchor parts respectively on the outer leads and also cutting off the plurality of outer leads and another tie bar 22 connected to the lead frame 2 to thereby form a primary molded body 5; and forming a secondary molded body by forming a second sealed body 6 with a sealing resin so as to cover the anchor parts and the first sealed body 4 of the primary molded body 5.
(FR) Selon la présente invention, un dispositif à semi-conducteur (1) est fabriqué : en préparant une grille de connexion (2) dans laquelle une pluralité de régions formant un motif de circuit (20) sont formées côte à côte; en fixant des composants électroniques sur les régions formant un motif de circuit (20) afin de former une unité de circuit électronique (3); en formant un premier corps étanche (4) avec une résine d'étanchéité de telle sorte que l'unité de circuit électronique (3) soit couverte et qu'une pluralité de fils externes soient exposés; en découpant une partie d'une barre de liaison (23) reliant la pluralité de fils externes afin de former ainsi des parties d'ancrage respectivement sur les fils externes et en découpant également la pluralité de fils externes et une autre barre de liaison (22) reliée à la grille de connexion (2) afin de former ainsi un corps moulé primaire (5); et en formant un corps moulé secondaire en formant un second corps étanche (6) avec une résine d'étanchéité de sorte à recouvrir les parties d'ancrage et le premier corps étanche (4) du corps moulé primaire (5).
(JA) 複数の回路パターン形成領域20が並んで形成されたリードフレーム2を準備し、回路パターン形成領域20に電子部品を取り付けて電子回路部3を形成し、電子回路部3を覆うと共に複数のアウターリードが露出するように、封止樹脂によって第1の封止体4を形成し、複数のアウターリードを繋ぐタイバー23の一部を切断してアウターリードのそれぞれにアンカ部を形成すると共にリードフレーム2と繋がる他のタイバー22と複数のアウターリードとを切断して一次成形体5を形成し、一次成形体5の第1の封止体4及びアンカ部を覆うように封止樹脂によって第2の封止体6を形成して二次成形体を形成して半導体装置1を製造する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)