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1. (WO2018017282) TECHNIQUES TO PROVIDE A MULTI-LEVEL MEMORY ARCHITECTURE VIA INTERCONNECTS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/017282 International Application No.: PCT/US2017/038872
Publication Date: 25.01.2018 International Filing Date: 22.06.2017
IPC:
H03M 7/30 (2006.01) ,G06F 3/06 (2006.01) ,H04B 10/25 (2013.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
7
Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information is represented by a different sequence or number of digits
30
Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
10
Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
25
Arrangements specific to fibre transmission
Applicants: INTEL CORPORATION[US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors: NACHIMUTHU, Murugasamy K.; US
KUMAR, Mohan J.; US
Agent: DYER, Richard A.; US
Priority Data:
15/476,89631.03.2017US
62/365,96922.07.2016US
62/376,85918.08.2016US
62/427,26829.11.2016US
Title (EN) TECHNIQUES TO PROVIDE A MULTI-LEVEL MEMORY ARCHITECTURE VIA INTERCONNECTS
(FR) TECHNIQUES PERMETTANT DE FOURNIR UNE ARCHITECTURE DE MÉMOIRE MULTI-NIVEAUX PAR L'INTERMÉDIAIRE D'INTERCONNEXIONS
Abstract:
(EN) Various embodiments are generally directed to an apparatus, method and other techniques to enable memory interfaces to communicate read request, write requests, and data via an interconnect. Embodiments, include processing write requests to write data into memory coupled via an interconnect and processing read requests to read data from memory coupled via an interconnect. In embodiments, the data may be compressed data based on a compression mechanism and communicated in a fabric packet including a compression mechanism indicator, the compressed data, and an address, the compression mechanism indicator to indicate which compression mechanism is applied to the data.
(FR) L'invention concerne généralement divers modes de réalisation d'un appareil, d'un procédé et d'autres techniques permettant à des interfaces de mémoire de communiquer une demande de lecture, des demandes d'écriture et des données par l'intermédiaire d'une interconnexion. Des modes de réalisation comprennent le traitement de demandes d'écriture pour écrire des données dans une mémoire couplée par l'intermédiaire d'une interconnexion et le traitement de demandes de lecture pour lire des données à partir de la mémoire couplée par l'intermédiaire d'une interconnexion. Dans des modes de réalisation, les données peuvent être des données compressées basées sur un mécanisme de compression et communiquées dans un paquet de matrice de commutation comprenant un indicateur de mécanisme de compression, les données compressées et une adresse, l'indicateur du mécanisme de compression étant destiné à indiquer quel mécanisme de compression est appliqué aux données.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)