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1. (WO2018016178) SHIFT REGISTER CIRCUIT AND DISPLAY PANEL
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Pub. No.: WO/2018/016178 International Application No.: PCT/JP2017/019541
Publication Date: 25.01.2018 International Filing Date: 25.05.2017
IPC:
G11C 19/28 (2006.01) ,G09G 3/20 (2006.01) ,G09G 3/36 (2006.01) ,H03K 17/30 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
19
Digital stores in which the information is moved stepwise, e.g. shift registers
28
using semiconductor elements
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
30
Modifications for providing a predetermined threshold before switching
Applicants: MITSUBISHI ELECTRIC CORPORATION[JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors: ONO Takeshi; JP
AGARI Masafumi; JP
FUJINO Toshiaki; JP
KAWABUCHI Shinji; JP
Agent: YOSHITAKE Hidetoshi; JP
ARITA Takahiro; JP
Priority Data:
2016-14216620.07.2016JP
Title (EN) SHIFT REGISTER CIRCUIT AND DISPLAY PANEL
(FR) CIRCUIT DE REGISTRE À DÉCALAGE ET PANNEAU D'AFFICHAGE
(JA) シフトレジスタ回路および表示パネル
Abstract:
(EN) The purpose of the present invention is to provide a shift register circuit and a display panel that appropriately control the back-gate voltage of a transistor using a simple configuration at low cost. Each of a plurality of shift register SR in a shift register circuit 1 includes an output circuit 100, a charge-discharge circuit 200, a first power supply terminal S2 for supplying the charge-discharge circuit 200 with a constant voltage, and at least one back-gate voltage generation circuit 300. The output circuit 100 or the charge-discharge circuit 200 includes at least one transistor Q1 having a back-gate electrode. The back-gate voltage generation circuit 300 includes a back-gate node N2. The back-gate node N2 is connected to the back-gate electrode of the transistor Q1. The back-gate voltage generation circuit 300 changes the voltage of the back-gate node N2 in accordance with the voltage of the gate electrode of the transistor Q1, and the first power supply terminal S2 supplies the back-gate voltage generation circuit 300 with a drive voltage.
(FR) Le but de la présente invention est de fournir un circuit de registre à décalage et un panneau d'affichage qui commandent de manière appropriée la tension de grille arrière d'un transistor en utilisant une configuration simple à faible coût. Chaque registre à décalage (SR) d'une pluralité de registres à décalage (SR) dans un circuit de registre à décalage (1) comprend un circuit de sortie (100), un circuit de charge-décharge (200), une première borne d'alimentation électrique (S2) destinée à alimenter le circuit de charge-décharge (200) avec une tension constante, et au moins un circuit de génération de tension de grille arrière (300). Le circuit de sortie (100) ou le circuit de charge-décharge (200) comprend au moins un transistor (Q1) ayant une électrode de grille arrière. Le circuit de génération de tension de grille arrière (300) comprend un nœud de grille arrière (N2). Le nœud de grille arrière (N2) est connecté à l'électrode de grille arrière du transistor (Q1). Le circuit de génération de tension de grille arrière (300) change la tension du nœud de grille arrière (N2) en fonction de la tension de l'électrode de grille du transistor (Q1), et la première borne d'alimentation électrique (S2) alimente le circuit de génération de tension de grille arrière (300) avec une tension de commande.
(JA) 本発明はトランジスタのバックゲート電圧を簡易な構成かつ抵コストで適切に制御するシフトレジスタ回路および表示パネルの提供を目的とする。シフトレジスタ回路1において、複数の単位シフトレジスタSRのそれぞれは、出力回路100、充放電回路200、充放電回路200に定電圧を供給する第1の電源端子S2、少なくとも1つのバックゲート電圧生成回路300を備え、出力回路100又は充放電回路200は、バックゲート電極を備えた少なくとも1つのトランジスタQ1を備え、バックゲート電圧生成回路300はバックゲート用ノードN2を備え、バックゲート用ノードN2は、トランジスタQ1のバックゲート電極に接続され、バックゲート電圧生成回路300は、トランジスタQ1のゲート電極の電圧に応じてバックゲート用ノードN2の電圧を変化させ、バックゲート電圧生成回路300には、第1の電源端子S2から駆動電圧が供給される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)