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1. (WO2018014792) PASSIVATION LAYER MANUFACTURING METHOD, HIGH-VOLTAGE SEMICONDUCTOR POWER DEVICE AND FRONT ELECTRODE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/014792 International Application No.: PCT/CN2017/093002
Publication Date: 25.01.2018 International Filing Date: 14.07.2017
IPC:
H01L 21/56 (2006.01) ,H01L 23/29 (2006.01) ,H01L 23/31 (2006.01) ,H01L 23/48 (2006.01) ,H01L 21/285 (2006.01)
Applicants: GLOBAL ENERGY INTERCONNECTION RESEARCH INSTITUTE CO., LTD[CN/CN]; 18 Binhe Ave., Future Science Park, Changping District, Beijing 102209, CN
Inventors: JIN, Rui; CN
PAN, Yan; CN
WEN, Jialiang; CN
ZHAO, Yan; CN
GAO, Mingchao; CN
WU, Di; CN
HE, Yanqiang; CN
LIU, Jiang; CN
CUI, Lei; CN
Agent: CHINA PAT INTELLECTUAL PROPERTY OFFICE; 2nd Floor, Zhongguancun Intellectual Property Building, Block B No.21 Haidian South Road, Haidian Beijing 100080, CN
Priority Data:
201610704091.623.08.2016CN
201610843019.122.09.2016CN
201620769675.720.07.2016CN
Title (EN) PASSIVATION LAYER MANUFACTURING METHOD, HIGH-VOLTAGE SEMICONDUCTOR POWER DEVICE AND FRONT ELECTRODE
(FR) PROCÉDÉ DE FABRICATION DE COUCHE DE PASSIVATION, DISPOSITIF D'ALIMENTATION À SEMI-CONDUCTEUR HAUTE TENSION, ET ÉLECTRODE AVANT
(ZH) 钝化层制造方法及高压半导体功率器件、正面电极
Abstract: front page image
(EN) A planar terminal passivation method, a semiconductor power device and a front electrode. The method comprises successively depositing a dielectric layer (5), a glass passivation layer (6) and a polyimide protection layer (8) onto a semiconductor power device to form a plurality of composite passivation layers. The semiconductor power device is manufactured by using this method.
(FR) L'invention concerne un procédé de passivation de borne plane, un dispositif d'alimentation à semi-conducteur et une électrode avant. Le procédé comprend le dépôt successif d'une couche diélectrique (5), d'une couche de passivation en verre (6) et d'une couche de protection en polyimide (8) sur un dispositif d'alimentation à semi-conducteur pour former une pluralité de couches de passivation composites. Le dispositif d'alimentation à semi-conducteur est fabriqué selon ce procédé.
(ZH) 一种平面终端钝化方法及半导体功率器件、正面电极,所述方法包括在半导体功率器件上顺次淀积介质层(5)、玻璃钝化层(6)和聚酰亚胺保护层(8),形成多层复合钝化层;半导体功率器件采用上述方法制造。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)