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1. (WO2018013695) A STANDARD CELL ARCHITECTURE FOR REDUCED LEAKAGE CURRENT AND IMPROVED DECOUPLING CAPACITANCE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/013695 International Application No.: PCT/US2017/041721
Publication Date: 18.01.2018 International Filing Date: 12.07.2017
Chapter 2 Demand Filed: 02.05.2018
IPC:
H01L 27/02 (2006.01) ,H01L 27/118 (2006.01) ,H01L 27/092 (2006.01) ,H03K 19/177 (2006.01) ,H03K 19/00 (2006.01) ,H03K 19/003 (2006.01)
Applicants: QUALCOMM INCORPORATED[US/US]; ATTEN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors: SAHU, Satyanarayana; US
CHEN, Xiangdong; US
VILANGUDIPITCHAI, Ramaprasath; US
KUMAR, Dorav; US
Agent: HODGES, Jonas J.; US
GELFOUND, Craig A.; US
HARRIMAN, John D.; US
BINDSEIL, James; US
Priority Data:
15/209,65013.07.2016US
Title (EN) A STANDARD CELL ARCHITECTURE FOR REDUCED LEAKAGE CURRENT AND IMPROVED DECOUPLING CAPACITANCE
(FR) ARCHITECTURE DE CELLULE STANDARD POUR COURANT DE FUITE RÉDUIT ET CAPACITÉ DE DÉCOUPLAGE AMÉLIORÉE
Abstract: front page image
(EN) A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.
(FR) Cette invention concerne un circuit intégré de cellule standard, comprenant éventuellement une pluralité de transistors pMOS dont chacun comprend un drain de transistor pMOS, une source de transistor pMOS et une grille de transistor pMOS. Chaque drain de transistor pMOS et chaque source de transistor pMOS de la pluralité de transistors pMOS peut être couplé(e) à une première source de tension. Le circuit intégré de cellule standard comprend en outre éventuellement une pluralité de transistors nMOS comprenant chacun un drain de transistor nMOS, une source de transistor nMOS et une grille de transistor nMOS. Chaque drain de transistor nMOS et chaque source de transistor nMOS de la pluralité de transistors nMOS est couplé(e) à une seconde source de tension inférieure à la première source de tension.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)