Search International and National Patent Collections

1. (WO2018013156) CLOCK ADJUSTMENT FOR VOLTAGE DROOP

Pub. No.:    WO/2018/013156    International Application No.:    PCT/US2016/051814
Publication Date: Fri Jan 19 00:59:59 CET 2018 International Filing Date: Fri Sep 16 01:59:59 CEST 2016
IPC: G06F 11/07
G06F 11/30
Applicants: ADVANCED MICRO DEVICES, INC.
Inventors: KOMMRUSCH, Steven
MEHRA, Amitabh
BORN, Richard Martin
YOUNG, Bobby D.
Title: CLOCK ADJUSTMENT FOR VOLTAGE DROOP
Abstract:
A processor (100) adjusts frequencies of one or more clock signals (230) in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals (220, 221, 222, 223, 224, 225, 226, 227), each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.