Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018009171) RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE SIGNALING
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2018/009171 International Application No.: PCT/US2016/040912
Publication Date: 11.01.2018 International Filing Date: 02.07.2016
IPC:
H01L 25/065 (2006.01) ,H01L 23/60 (2006.01) ,H01L 23/498 (2006.01) ,H01L 23/525 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
60
Protection against electrostatic charges or discharges, e.g. Faraday shields
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
525
with adaptable interconnections
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
AYGUN, Kemal [US/US]; US
DISCHLER, Richard J. [US/US]; US
MORRISS, Jeff C. [US/US]; US
QIAN, Zhiguo [CN/US]; US
GOMES, Wilfred [IN/US]; US
ZHANG, Yu Amos [CN/US]; US
VISWANATH, Ram S. [US/US]; US
SWAMINATHAN, Rajasekaran Raja [IN/US]; US
SRINIVASAN, Sriram [IN/US]; US
MEKONNEN, Yidnekachew S. [US/US]; US
GANESAN, Sanka Gans [US/US]; US
ROYTMAN, Eduard [US/US]; US
MANUSHAROW, Mathew J. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 94054, US
Inventors:
AYGUN, Kemal; US
DISCHLER, Richard J.; US
MORRISS, Jeff C.; US
QIAN, Zhiguo; US
GOMES, Wilfred; US
ZHANG, Yu Amos; US
VISWANATH, Ram S.; US
SWAMINATHAN, Rajasekaran Raja; US
SRINIVASAN, Sriram; US
MEKONNEN, Yidnekachew S.; US
GANESAN, Sanka Gans; US
ROYTMAN, Eduard; US
MANUSHAROW, Mathew J.; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) RLINK - DIE TO DIE CHANNEL INTERCONNECT CONFIGURATIONS TO IMPROVE SIGNALING
(FR) CONFIGURATIONS D'INTERCONNEXION DE CANAUX DE PUCE À PUCE À LIAISON R POUR AMÉLIORER LA SIGNALISATION
Abstract:
(EN) Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
(FR) L'invention concerne des configurations d'interconnexion de canaux de puce à puce de puce de circuit intégré (CI) (leurs systèmes et procédés de fabrication) qui peuvent améliorer la signalisation vers et à travers un canal de communication de signaux de données de bus à extrémité unique en incluant des structures d'induction sur puce; des caractéristiques d'interconnexion sur puce; des modèles de bosses de puce de premier niveau sur boîtier et des structures de treillis de mise à la terre; des lignes de transmission de signaux de données horizontales haute vitesse sur boîtier; des interconnexions de transmission de signaux de données verticales sur boîtier; et/ou des connecteurs électro-optiques (EO) sur boîtier dans diverses configurations d'interconnexion de puce à puce pour des connexions de signaux améliorées et une transmission par l'intermédiaire d'un canal de signaux de données s'étendant à travers un ou plusieurs dispositifs de boîtier de dispositif à semi-conducteur, qui peuvent comprendre un connecteur électro-optique (EO) sur lequel peut être monté au moins un dispositif de boîtier, et/ou des boîtiers de dispositif à semi-conducteur dans une configuration de boîtier sur boîtier.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)