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1. (WO2018008529) SILICON CARBIDE SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/008529 International Application No.: PCT/JP2017/023990
Publication Date: 11.01.2018 International Filing Date: 29.06.2017
IPC:
H01L 29/06 (2006.01) ,H01L 29/12 (2006.01) ,H01L 29/47 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/861 (2006.01) ,H01L 29/868 (2006.01) ,H01L 29/872 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
47
Schottky barrier electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
868
PIN diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
872
Schottky diodes
Applicants: DENSO CORPORATION[JP/JP]; 1-1, Showa-cho, Kariya-city, Aichi 4488661, JP
TOYOTA JIDOSHA KABUSHIKI KAISHA[JP/JP]; 1, Toyota-cho, Toyota-shi, Aichi 4718571, JP
Inventors: TAKEUCHI Yuichi; JP
MITANI Shuhei; JP
SUZUKI Katsumi; JP
YAMASHITA Yusuke; JP
Agent: YOU-I PATENT FIRM; Nagoya Nishiki City Bldg. 4F 1-6-5, Nishiki, Naka-ku, Nagoya-shi, Aichi 4600003, JP
Priority Data:
2016-13367605.07.2016JP
Title (EN) SILICON CARBIDE SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR
(FR) DISPOSITIF SEMI-CONDUCTEUR AU CARBURE DE SILICIUM ET SON PROCÉDÉ DE PRODUCTION
(JA) 炭化珪素半導体装置およびその製造方法
Abstract:
(EN) The widths of p-type guard rings (21) are set in accordance with the intervals between adjacent p-type guard rings (21), and the widths increase as the intervals between the p-type guard rings (21) become larger. Furthermore, the width of frame-like parts (32) is set so as to be essentially equal to the width of p-type deep layers (5), and the interval between the frame-like parts (32) is set so as to be equal to the interval between the p-type deep layers (5). Accordingly, the differences between the formation areas of trenches (5a, 21a, 30a) per unit area in a cell section, a connecting section, and a guard ring section, can be reduced. Therefore, when a p-type layer (50) is formed, the differences between the amounts of the p-type layer (50) entering the trenches (5a, 21a, 30a) per unit area can also be reduced, and the thickness of the p-type layer (50) can be made uniform.
(FR) Selon la présente invention, les largeurs d'anneaux de garde de type p (21) sont établies en fonction des intervalles entre des anneaux de garde de type p adjacents (21), et les largeurs augmentent à mesure que les intervalles entre les anneaux de garde de type p (21) deviennent plus importants. En outre, la largeur des parties en forme de cadre (32) est établie de manière à être sensiblement égale à la largeur des couches profondes de type p (5), et l'intervalle entre les parties en forme de cadre (32) est établi de manière à être égal à l'intervalle entre les couches profondes de type p (5). En conséquence, les différences entre les zones de formation de tranchées (5a, 21a, 30a) par unité de surface dans une section de cellule, une section de connexion et une section d'anneau de garde peuvent être réduites. Par conséquent, lorsqu'une couche de type p (50) est formée, les différences entre les quantités de la couche de type p (50) entrant dans les tranchées (5a, 21a, 30a) par unité de surface peuvent également être réduites, et l'épaisseur de la couche de type p (50) peut être rendue uniforme.
(JA) p型ガードリング(21)の幅を隣り合うp型ガードリング(21)同士の間隔に合わせて設定し、p型ガードリング(21)同士の間隔が大きくなるほど幅が大きくなるようにする。また、枠状部(32)の幅を基本的にはp型ディープ層(5)の幅と等しくして枠状部(32)同士の間隔をp型ディープ層(5)同士の間隔と等しくする。これにより、セル部と繋ぎ部およびガードリング部において、単位面積当たりのトレンチ(5a、21a、30a)の形成面積の差を小さくできる。したがって、p型層(50)を形成する際に、単位面積当たりのトレンチ(5a、21a、30a)内に入り込むp型層(50の量の差も小さくなり、p型層(50)の厚みを均一化できる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)