Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018008527) SILICON CARBIDE SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2018/008527 International Application No.: PCT/JP2017/023988
Publication Date: 11.01.2018 International Filing Date: 29.06.2017
IPC:
H01L 29/06 (2006.01) ,H01L 29/12 (2006.01) ,H01L 29/47 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/861 (2006.01) ,H01L 29/868 (2006.01) ,H01L 29/872 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
47
Schottky barrier electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
868
PIN diodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
86
controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861
Diodes
872
Schottky diodes
Applicants:
株式会社デンソー DENSO CORPORATION [JP/JP]; 愛知県刈谷市昭和町1丁目1番地 1-1, Showa-cho, Kariya-city, Aichi 4488661, JP
トヨタ自動車株式会社 TOYOTA JIDOSHA KABUSHIKI KAISHA [JP/JP]; 愛知県豊田市トヨタ町1番地 1, Toyota-cho, Toyota-shi, Aichi 4718571, JP
Inventors:
竹内 有一 TAKEUCHI Yuichi; JP
鈴木 克己 SUZUKI Katsumi; JP
渡辺 行彦 WATANABE Yukihiko; JP
Agent:
特許業務法人ゆうあい特許事務所 YOU-I PATENT FIRM; 愛知県名古屋市中区錦一丁目6番5号 名古屋錦シティビル4階 Nagoya Nishiki City Bldg. 4F 1-6-5, Nishiki, Naka-ku, Nagoya-shi, Aichi 4600003, JP
Priority Data:
2016-13367505.07.2016JP
Title (EN) SILICON CARBIDE SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR
(FR) DISPOSITIF SEMI-CONDUCTEUR AU CARBURE DE SILICIUM ET SON PROCÉDÉ DE PRODUCTION
(JA) 炭化珪素半導体装置およびその製造方法
Abstract:
(EN) All of the intervals between adjacent p-type guard rings (21) are made to be equal to or smaller than the interval between p-type deep layers (5). As a result, the intervals between the p-type guard rings (21) become larger, i.e. trenches (21a) become less dense, and thus a p-type layer (50) can be inhibited from being formed thick in a guard ring section when grown epitaxially. Accordingly, if the p-type layer (50) in a cell section is to be removed during etching back, the p-type layer (50) can be removed without leaving residue in the guard ring section. Therefore, when the p-type layer (50) is etched back and the p-type deep layers (5), the p-type guard rings (21), and p-type connecting layers (30) are formed, residue of the p-type layer (50) can be inhibited from being left in the guard ring section.
(FR) L'invention concerne un dispositif semi-conducteur dans lequel tous les intervalles entre les anneaux de protection de type p adjacents (21) sont conçus pour être égaux ou inférieurs à l'intervalle entre les couches profondes de type p (5). En conséquence, les intervalles entre les anneaux de protection de type p (21) deviennent plus importants, c'est-à-dire que les tranchées (21a) deviennent moins denses, ce qui permet d'empêcher la formation en épaisseur d'une couche de type p (50) dans une section d'anneau de protection lorsqu'elle est développée de manière épitaxiale. Par conséquent, si la couche de type p (50) dans une section de cellule doit être retirée pendant la gravure en retrait, la couche de type p (50) peut être retirée sans que du résidu reste dans la section d'anneau de protection. De ce fait, lorsque la couche de type p (50) est gravée en retrait et que les couches profondes de type p (5), les anneaux de protection de type p (21) et des couches de liaison de type p (30) sont formés, il est possible d'empêcher que du résidu de la couche de type p (50) reste dans la section d'anneau de protection.
(JA) 隣り合うp型ガードリング(21)同士の間隔がすべてp型ディープ層(5)同士の間隔以下となるようにする。これにより、p型ガードリング(21)の間隔が大きくなること、つまりトレンチ(21a)が疎となることによって、p型層(50)をエピタキシャル成長させたときにガードリング部で厚く形成されることを抑制できる。したがって、エッチバック時にセル部のp型層(50)を除去すれば、ガードリング部においても残渣が残ることなくp型層(50)を除去することが可能になる。よって、p型層(50)をエッチバックしてp型ディープ層(5)やp型ガードリング(21)およびp型繋ぎ層(30)を形成する際に、ガードリング部にp型層(50)の残渣が残ってしまうことを抑制できる。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN109417087