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1. (WO2018008222) METHOD FOR MANUFACTURING SILICON WAFER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2018/008222 International Application No.: PCT/JP2017/014947
Publication Date: 11.01.2018 International Filing Date: 12.04.2017
IPC:
H01L 21/324 (2006.01) ,C30B 29/06 (2006.01) ,C30B 33/02 (2006.01) ,H01L 21/322 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
324
Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
29
Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
02
Elements
06
Silicon
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
33
After-treatment of single crystals or homogeneous polycrystalline material with defined structure
02
Heat treatment
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
322
to modify their internal properties, e.g. to produce internal imperfections
Applicants:
株式会社SUMCO SUMCO CORPORATION [JP/JP]; 東京都港区芝浦一丁目2番1号 1-2-1, Shibaura, Minato-ku, Tokyo 1058634, JP
Inventors:
松山 博行 MATSUYAMA Hiroyuki; JP
Agent:
特許業務法人樹之下知的財産事務所 KINOSHITA & ASSOCIATES; 東京都杉並区荻窪五丁目26番13号 3階 3rd Floor, 26-13, Ogikubo 5-chome, Suginami-ku, Tokyo 1670051, JP
Priority Data:
2016-13593808.07.2016JP
Title (EN) METHOD FOR MANUFACTURING SILICON WAFER
(FR) PROCÉDÉ DE FABRICATION D'UNE TRANCHE DE SILICIUM
(JA) シリコンウェーハの製造方法
Abstract:
(EN) This method for manufacturing a silicon wafer includes: a growing step for growing, by means of a Czochralski method, a silicon single crystal not containing crystal-originated particles (COP) and dislocation clusters; an oxidation-induced stacking fault (OSF) evaluation step for evaluating the OSF occurrence status of an evaluation wafer obtained from the silicon single crystal; and a heat treatment step for performing, under the condition of 1,310°C or higher, rapid thermal oxidation (RTO) treatment with respect to a silicon wafer obtained from the same silicon single crystal from which the evaluation wafer has been obtained, in the cases where the evaluation wafer has an OSF, and performing the RTO treatment under the condition below 1,310°C with respect to the silicon wafer in the cases where the evaluation wafer does not have the OSF.
(FR) La présente invention concerne un procédé de fabrication d'une tranche de silicium, comprenant: un étape de croissance consistant à faire croître, au moyen d'un procédé de Czochralski, un monocristal de silicium ne contenant pas de particules issues de cristaux (COP) et de amas de dislocations; une étape d'évaluation de défauts d'empilement induits par oxydation (OSF) consistant à évaluer l'état d'occurrence d'OSF d'une tranche d'évaluation obtenue à partir du monocristal de silicium; et un étape de traitement thermique consistant à effectuer, sous une condition supérieure ou égale à 1310°C, un traitement d'oxydation thermique rapide (RTO) par rapport à une tranche de silicium obtenue à partir du même monocristal de silicium à partir duquel a été obtenue la tranche d'évaluation, dans les cas où la tranche d'évaluation présente un OSF, et à effectuer le traitement de RTO sous une condition inférieure à 1310°C par rapport à la tranche de silicium dans les cas où la tranche d'évaluation ne présente pas d'OSF.
(JA) シリコンウェーハの製造方法は、チョクラルスキー法により、COPおよび転位クラスターを含まないシリコン単結晶を育成する育成工程と、シリコン単結晶から取得された評価ウェーハのOSFの発生状況を評価するOSF評価工程と、評価ウェーハにOSFが存在する場合、評価ウェーハと同じシリコン単結晶から取得されたシリコンウェーハに対し1310℃以上の条件でRTO処理を行い、評価ウェーハにOSFが存在しない場合、シリコンウェーハに対し1310℃未満の条件でRTO処理を行う熱処理工程とを含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
KR1020190002673DE112017003457CN109478512