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1. (WO2018005763) FIN FIELD EFFECT TRANSISTOR (FINFET) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS EMPLOYING SINGLE AND DOUBLE DIFFUSION BREAKS FOR INCREASED PERFORMANCE
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Pub. No.: WO/2018/005763 International Application No.: PCT/US2017/039941
Publication Date: 04.01.2018 International Filing Date: 29.06.2017
Chapter 2 Demand Filed: 19.04.2018
IPC:
H01L 29/78 (2006.01) ,H01L 21/8238 (2006.01) ,H01L 27/092 (2006.01) ,H01L 21/762 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
YUAN, Jun; US
LIU, Yanxiang; US
RIM, Kern; US
Agent:
AYCOCK, Bradley, R.; US
DAVENPORT, Taylor, M.; US
Priority Data:
15/197,94930.06.2016US
Title (EN) FIN FIELD EFFECT TRANSISTOR (FINFET) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS EMPLOYING SINGLE AND DOUBLE DIFFUSION BREAKS FOR INCREASED PERFORMANCE
(FR) CIRCUITS À SEMI-CONDUCTEUR À OXYDE MÉTALLIQUE COMPLÉMENTAIRE (CMOS) À TRANSISTOR À EFFET DE CHAMP À AILETTES (FINFET) UTILISANT DES RUPTURES DE DIFFUSION UNIQUE ET DOUBLE POUR UNE PERFORMANCE ACCRUE
Abstract:
(EN) Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.
(FR) L'invention concerne des circuits à semi-conducteur à oxyde métallique complémentaire (CMOS) à transistor à effet de champ (FET) à ailettes (FinFET) utilisant des ruptures de diffusion unique et double pour une performance accrue. Selon un aspect, un circuit CMOS FinFET utilisant des ruptures de diffusion unique et double comprend un FinFET de type P qui comprend une première ailette constituée d'un substrat semi-conducteur et correspondant à une région de diffusion de type P. Le circuit CMOS FinFET comprend un FinFET de type N qui comprend une seconde ailette constituée du substrat semi-conducteur et correspondant à une région de diffusion de type N. Pour isoler électriquement le FinFET de type P, des première et seconde structures d'isolation à rupture de diffusion unique (SDB) sont formées dans la première ailette de part et d'autre d'une grille du FinFET de type P. Pour isoler électriquement le FinFET de type N, des première et seconde structures d'isolation à double rupture de diffusion (DDB) sont formées dans la seconde ailette de part et d'autre d'une grille du FinFET de type N.
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African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)