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1. (WO2018005516) ACCELERATED I3C MASTER STOP

Pub. No.:    WO/2018/005516    International Application No.:    PCT/US2017/039533
Publication Date: Fri Jan 05 00:59:59 CET 2018 International Filing Date: Wed Jun 28 01:59:59 CEST 2017
IPC: G06F 13/42
Applicants: QUALCOMM INCORPORATED
Inventors: PITIGOI-ARON, Radu
Title: ACCELERATED I3C MASTER STOP
Abstract:
Systems, methods, and apparatus for communication over a serial bus in accordance with an I3C protocol are described. A method performed at a master device includes causing a line driver to enter a high-impedance mode of operation, and receiving data from the serial bus. When a data line of the serial bus is in a high voltage state while a last bit of a data byte is being transmitted, the line may be configured for an open-drain mode of operation, and transmitting a START condition on the serial bus while the last bit of the data byte is being transmitted. When a plurality of data bytes is sequentially transmitted with last bits that cause a low voltage state, the line may be configured for an open-drain mode of operation, and transmitting a START condition on the serial bus after the last bit of the data byte is being transmitted.