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1. (WO2018005376) CVD BASED OXIDE-METAL MULTI STRUCTURE FOR 3D NAND MEMORY DEVICES
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Pub. No.: WO/2018/005376 International Application No.: PCT/US2017/039317
Publication Date: 04.01.2018 International Filing Date: 26.06.2017
IPC:
H01L 21/02 (2006.01) ,H01J 37/32 (2006.01) ,H01L 21/324 (2006.01) ,H01L 27/11551 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
J
ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
37
Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
32
Gas-filled discharge tubes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
324
Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
Applicants:
APPLIED MATERIALS, INC. [US/US]; 3050 Bowers Avenue Santa Clara, California 95054, US
Inventors:
SINGHA ROY, Susmit; US
CHAN, Kelvin; US
LE, Hien Minh; US
KAMATH, Sanjay; US
MALLICK, Abhijit Basu; US
GANDIKOTA, Srinivas; US
JANAKIRAMAN, Karthik; US
Agent:
PATTERSON, B. Todd; US
TACKETT, Keith M.; US
Priority Data:
62/355,61128.06.2016US
Title (EN) CVD BASED OXIDE-METAL MULTI STRUCTURE FOR 3D NAND MEMORY DEVICES
(FR) MULTISTRUCTURES D’OXYDE DE MÉTAL À BASE DE DCPV POUR DISPOSITIFS DE MÉMOIRES NON-ET EN 3D
Abstract:
(EN) Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer, in one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases, in another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process, in another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.
(FR) La présente invention décrit généralement des modes de réalisation qui portent sur un procédé de formation d’une couche de métal et un procédé de formation d’une couche d’oxyde sur la couche de métal, selon un mode de réalisation, la couche de métal est formée sur une couche de germe, et la couche de germe aide le métal dans la couche de métal à nucléer avec une petite taille de grains sans affecter la conductivité de la couche de métal. La couche de métal peut être formée par dépôt chimique en phase vapeur amélioré par plasma (PECVD) et de l’azote gazeux peut être injecté dans la chambre de traitement en même temps que les gaz précurseurs, selon un autre mode de réalisation, une couche de barrière est formée sur la couche de métal afin de prévenir l’oxydation de la couche de métal pendant le processus ultérieur de dépôt de la couche d’oxyde, selon un autre mode de réalisation, la couche de métal est traitée avant le dépôt de la couche d’oxyde afin de prévenir l’oxydation de la couche de métal.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)